F: References

Chapter F: Multi Chip Modules

F4. Level 4. References

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F4.1 Recommended reading

"Electronic Components, Packaging and Production" ISBN:82-992193-2-9, by Leif Halbo and Per Øhlckers

"Electronic Materials Handbook, Volume 1 Packaging", ASME International, 1989

"Plastics for Electronics", M. T. Goosey, Elsevier Applied Science Publishers, 1985

"Chip on Board Technologies for Multi Chip Modules", J. H. Lau, Van Nostrand Reinhold, 1994

"Introduction to Multi Chip Modules", N. Sherwani, Q. Yu and S. Badida, John Wiley & Sons, 1995

F4.2 General references

[F1] B. McDermott, "Shifting the Paradigm", Circuitree, March 1996

[F2] P. D. Knudsen, R. L. Brainard and K. T. Schell, "A Photoimageable Dielectric for Sequential PWB Fabrication", Circuit World, Vol. 21, No. 3, 1995

[F3] Giuseppe Vendramin and Mike Weller, "MCM-L Rethinking Electronic Packaging", IBM Corporation

[F4] B. V. Fasano, R. Indyk, D. O'Conner, A. L. Plachy, S. N. S. Reddy, "Glass Ceramic Substrates for Flip Chip Packages", IBM Corporation, East Fishkill, New York

[F5] Kuracina, R., "Flip Chip Packaging for the Year 2000", Presented at Semicon West '98, to be published

[F6] DiGiacomo, G., "Reliability of Electronic Packages and Semiconductor Devices", McGraw-Hill, 1996

[F7] Sylvester, Mark F., Banks, Donald R., Kern Richard L., and Pofahl, Ronald G., "Thermomechanical Reliability Assessment of Large Organic Flip-Chip Ball Grid Array Packages", 1998 Proceedings, 48th Annual Electronic Components and Technology Conference, pp. 851-860

F4.3 Table index

Table 1 Acronym list MCM *

Table 2: Laser parameters *

Table 3: Properties for different via-hole techniques *

Table 4: Typical properties of adhesive flexible base material *

Table 5: Comparison of different substrate materials for MCM-L *

Table 6: Typical wire bond strengths for different metallisation systems *

Table 7: Comparison of dielectrics used for SBU technology *

Table 8: Overview of different Build Up technologies, with type of dielectrics and minimum feature sizes. *

Table 9: The design rules for Matsushita ALIVH technology *

Table 10 Properties of substrate materials for hybrid technology, and other important properties (In: inorganic, Semi: semiconductor, P: plastic) *

Table 11 Properties of thickfilm conductor systems *

Table 12 Typical properties of thick film resistors *

Table 13 Typical properties of printed and discrete capacitors *

Table 14 Properties of alumina-based high-temperature multilayer ceramic *

Table 15 Properties of low-temperature multilayer ceramic *

Table 16 Resistor Performance - Resistance and TCR *

Table 17 Physical Properties *

Table 18 Properties of thin film resistors *

Table 19 The key features of the multilayer ceramic substrate. *

Table 20 Dimensional features of the ceramic substrate *

Table 21 Electrical performance of the multilayer glass ceramic compared to that of alumina ceramic. *

Table 22 Comparison of thin film packages used in various IBM systems. *

F4.4 Figure index

Figure 1. The data for MCM and MCP regional growth by revenue show that grow is shifting away from the U.S. and into Europe and Asia over the next five to seven years. Source: BPA Associates and Electronic Trends. *

Figure 2. A laser drilled via in polyimide dielectric *

Figure 3: Cross-section of metalised laser-drilled via *

Figure 4: "Cutaway" of two-layer metallisation *

Figure 5: Different technology choices available for SBU *

Figure 6. IBMs MCM-L SRAM *

Figure 7. Packaging multiple ASICs in bare die format results in significant real estate savings. *

Figure 8. MCM-L combining flip-chip technology on Microvia substrate. *

Figure 9: A schematic drawing of the ALIVH technology from Matsushita. *

Figure 10 Cross section of an ALIVE circuit board used in the NTT P201 Hyper Digital Phone. *

Figure 11 The SBU board used in the Casio MR-80 radio *

Figure 12 A cross-section of the SBU board and the flip chip die attach used by Casio. *

Figure 13 The SBU boards used in the Sony DCR-PC7 Camcorder folded out. *

Figure 14 A cross section of the SBU board and a BGA component. *

Figure 15 A close up of the cross section of the SBU board. The board has four core layers, and two build up dielectric layers at each side. *

Figure 16 Typical temperature profile for thick film firing *

Figure 17 Thick film resistor with termination *

Figure 18 Process flow for production of thick film circuits *

Figure 19 Probe card for testing of thin and thick film MCMs *

Figure 20 Laser trim cut forms. a): L-cut, the most common, b): Top hat plunge cut, c): Digital trimming, which is most used for high precision resistors. *

Figure 21 Laser trimmer for thickfilm hybrid circuits, ESI Model 44 *

Figure 22 Process flow for mounting thick film hybrid circuits based on a) Bare-die, b)Soldering of packaged components. *

Figure 23 Production process for multilayer ceramic, schematically *

Figure 24 Combination of naked chips in cavities and soldered, packaged SMD components on multilayer ceramic module *

Figure 25 Process flow for production of thin film hybrid circuits *

Figure 26 Structure of thin film resistor with gold termination. *

Figure 27 Thin film transistors, structure *

Figure 28 AT&T´s structure for multilayer thin film *

Figure 29 Cross-section of Raychem´s High Density Interconnect (HDI) schematically and observed through microscope *

Figure 30 Elements of the design rules for Raychem´s HDI technology *

Figure 31 Cross-section of the S/390 G5 TSM thinfilm structure. The M0 thin film capture pad is shown overlaying the glass ceramic via. At the top of the film pattern is the M5. The M5 layer provides repair capability and chip connectivity. In between are the two mesh layers and X/Y plane pair. *

Figure 32 The TSM side of the S/390 G5 MCM after thin film completion are seen. The 29 chip sites and the de-coupling capacitor sites between the chip sites are clearly visible. The one site in the centre of the top row is used for thin film process control. *

Figure 33 The BSM side of the S/390 G5 MCM after gold pins have been brazed to the thin film I/O. In the center channel are thin film VPT pads used to test voltage planes and to distribute current to the TSM during the thin film plating process. *

Figure 34 A cross-section of a IBM multilayer ceramic – thin film module *