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Chapter F: Multi Chip Modules
F2. Level 2. Conclusions / Guidelines
Print this section in .pdf format by clicking the link There exist an increasing number of different MCM technologies. New processes and materials are continuously introduced, and many smaller or larger alterations are made to existing processes. Mixing of different technologies means that to some extent, the borders between different technologies are erased. One example is the introduction of the "Combi film" technology where thick and thin film techniques are mixed on the same circuit. In addition, the border between multi chip modules and PCB technology is to some extent wiped out with the new fine line (Sequential Build-Up, SBU) laminates. F2.1 MCM LWith over 16 million units being produced worldwide in 1997, multichip modules on laminate (MCM-L) are the fastest growing component of overall MCM sales. MCM-Ls are projected to comprise almost 70% of all MCMs produced by 2001. Initially popular in telecommunications, MCM-Ls are expected to grow in the automotive and office areas at greater than 25% compound annual growth rate (CAGR) over the next four years [1]. According to Technology Forecasters, MCM-L units produced in 1997 outweigh all other MCMs by about two to one. Clearly the infrastructure for ceramic MCMs has been in place long before laminates. In the mid-1970s, ceramic MCMs were capable of integrating over 100 chips on a single substrate. MCM-L solutions, however, are beginning to span a wide array of applications once reserved only for ceramics. A significant factor in this trend is the introduction of low-melt flip-chip processes. Flip-chip die can now be connected to laminate carriers using slightly modified surface mount processes. Advances in laminate structures, such as high-density Microvia substrates, have accommodated line widths and spacings down to 50 µm and vias down to 90 µm. This is significant for enabling the escape of the dense I/O grid of flip-chip die. The smaller vias and fine lines allow more signal lines to be routed between the pads, thereby reducing the overall number of layers required. Advancements in moisture sensitivity coupled with new underfill formulations have lead to robust designs. These designs can withstand factory conditions of 30°C and 60% relative humidity for up to one week and suffer no adverse effects during the subsequent second-level assembly processes. These advancements have afforded MCM-Ls the opportunity to fill requirements in mobile computing, automotive and RF applications. Microprocessors with L2 cache on laminate carriers are being used in laptop computers. In the last twelve months, three suppliers of automotive applications have developed MCM-L packages capable of surviving the harsh under-the-hood environment. With respect to RF packaging, the Semiconductor Industry Association (SIA) roadmap indicates the performance basis for selecting ceramic over plastic laminate will be reduced as improvements in high-performance plastics exhibit cost advantages over ceramics [3]. F2.1.1 Sequential Build Up Process The additive process of the SBU technology avoids the limitations inherent in the subtractive process that is used with the traditional laminates (pre laminated with copper foils). There is either any need for all the process chemistry involved in the plating of high aspect ratio through-holes in the traditional prosess. The different process steps are discussed in this section. F2.1.1.1 Via holes The main limitation to increased density of conventional circuit boards is area needed for via generation. In the SBU techniques, both the hole diameter as well as the annular ring diameter may be significantly smaller. The reduction in hole diameter is partly because of the thin dielectric layer and the hole forming techniques. The latter because there will be no miss-registration as it is with the conventional stacking of prepregs. A 250 mm drilled hole in a multilayer board will typically require a 625 mm via pad with a minimum hole to hole pitch of 750 mm. For SBU technology an inner layer hole diameter of less than 50 mm is currently in production.Three different techniques are used for creating the via-holes. These are photo-defined vias, laser-drilled vias and plasma-etch vias, each described underneath. F2.1.1.1.1 Photo defined via
F2.1.1.1.2 Laser drilling
Figure F2. A laser drilled via in polyimide dielectric. F2.1.1.1.3 Plasma etch
Table F3: Properties for different via-hole techniques.
F2.1.1.2 Flexible base materials Conventional flexible base materials are made by bonding the copper layer to the polyimide dielectrics with an adhesive. However, the use of an adhesive layer increases the z-axis thermal expansion of the laminate which can cause cracking of the through hole metallisation during thermal cycling. Eliminating the adhesive using adhesive-less flexible base material is the best way to minimise the cracking tendency. This can be obtained in three ways: F2.1.1.2.1 Chemical deposition The surface of the polyimide is prepared before a Ni and Cr is electroless deposited. Copper is then electrolytically plated up to the desired thickness. The nickel, which is used as an adhesive promoter, has to be removed in a second etching process after the copper when patterning. In addition, the nickel is quite brittle. F2.1.1.2.2 Vacuum deposition In vacuum deposition (evaporation or sputtering) a thin seed layer (adhesion promoter) of chromium is deposited on the foil, followed by copper. To obtain the wanted copper thickness, the additional copper is plated electrolytically. A typical problem with this technique is a drop in copper adhesion after thermal and pressure treatment. F2.1.1.2.3 Casting A not yet polymerised polyimide (in liquid form) is poured onto the copper foil, which is joined with the polyimide film. After polymerisation a single-sided flexible base material is formed. More layers are obtained by sintering together single sided sheets. There is no metallic adhesion promoters used in this process. Physical parameters like peel-strength, dimensional stability and dielectric constant are equal or better than for conventional flexible laminates. The homogenous dielectric material is well fitted for both plasma and laser drilling. Typical properties of adhesive flexible base material are shown in the table below. Table F4: Typical properties of adhesive flexible base material
F2.1.1.3 Resin filled Aramid-Paper base material (Thermount, Du Pont) Aramid is an organic compound, which can be produced in form of long filaments. In the woven form it is known as Kevlar. Filled with various resins like epoxy or polyimide it can be used as base material for PCB’s. The main properties is the negative expansion coefficient of aramid, which together with the resin gives a base material with a CTE which can be tailored to 4 – 8 ppm/K. This makes it a very good match to silicon. When the aramid is in the form of long fibres, it is very difficult to drill du to the strong fibres. This type of material has therefore disappeared from the market. However, in the non-woven form the material is very promising. As the material is pure organic, processing methods like laser and plasma can be used. F5: Comparison of different substrate materials for MCM-L
F2.1.2 Wire bonding on SBU The MCM-L and MCM-Flex have significantly softer dielectrics than most other MCM technologies. This means that a careful design of the bond pad and careful specification of the metallisation system. Also the bonding process is important.
Wire bonding typically requires between 100 and 1250 nm of soft gold on the bond pad. For thin layers (100 – 200 nm) immersion gold can be used. This process is self-limiting, and gold is plated on all exposed surfaces, after the solder mask has been applied. Once a complete gold coverage of the surface is achieved, the plating process stops. Immersion gold is the least expensive gold finish available. This coating is commonly used for ordinary surface mount assembly, and provides excellent solderability and coplanarity without a significant cost increase compared to other finishes. This means that the same finish can be used for both wirebonding and soldering. If higher gold thickness is needed (500 – 1000 nm) for gold wire bonding, electroless gold can be used. The electroless process means that all exposed metal surfaces will be plated. The process will continue as long as it immersed into the plating bath. However, this amount of gold will have a negative effect on the solder, causing a brittle joint. If thicker gold is needed, electroplating has to be used. Electroplated gold is selectively added onto the metal surfaces that are included in the external electrical circuit. This means that all wire bonding pads must be connected together in a bus. The electroplating is a more costly process, and the required bussing can cause some design (layout) problems The gold thickness influences on the wire bond pull strength. A study by McDermott [F1] is shown in the table below. In this study a 25 mm gold wire has been bonded onto different gold surfaces. In all cases a 5 mm nickel layer underneath the gold.Table F6: Typical wire bond strengths for different metallisation systems .
During the bonding process, under pressure and high temperature above the glass transition temperature the PCB will deform under the bond area often called cupping. This cupping effect will dissipate the ultrasonic energy, reducing the bond yield. However below Tg, the PCB is hard and rigid and gives few problems in the wire bonding process. The use of nickel under the gold finish increases the stiffness of the pad. In addition, the nickel acts as a diffusion barrier between the copper and gold. If the gold thickness is more than 1,25 mm, there is no need for the diffusion barrier. Other options to increase the stiffness and hardness is to use thin coatings of tungsten or titanium (30-50 nm).Higher Tg materials allows increased bond temperature (increased ultrasonic energy) without exceeding the glass transition temperature. Also a larger bonding pad will help dissipate the heat from the bond area and therefore reduce the localised temperature of the substrate under the bonding pad. The use of thinner wires will allow bonding with lower pressure and reduced cupping effect. F2.1.3 Dielectrics for SBUThe dielectric material used in sequential build up technology has to fulfil several requirements. These are
Table F7: Comparison of dielectrics used for SBU technology.
F2.1.3.1 Deposition of dielectrics The dielectric can be applied to the substrate in different ways [F2]. One is to move the substrate on a conveyor through a sprayed "curtain" of the dielectric. This method gives high transfer efficiency, however the thin layer of dielectric falling through the air gives a significant loss of solvent. Typically, thickness in the 25 to 60 mm can be obtained in this way.Spin coating is another option for deposition of dielectrics. This gives thinner layers, less than 20 mm. The transfer efficiency is however low. Nevertheless, this is the method of choice for high cost polyimide solutions, since the equipment is well characterised from the semiconductor industry.Spray coating has a potential efficiency in between curtain and spin coating. With a proper design of the equipment and the use of low pressure high volume spray, good coatings can be obtained. There is neither a need for high solvent dilution. Roller coating is an interesting approach, where both sides of the substrate can be coated in the same process. The application of the dielectric in the form of dry films has significant drawbacks as poor conformity to varied surface topography, loss of possibility of customised thickness and high cost. The use of photoimageable dielectrics causes a significant reduction in the number of process steps. The result is also less waste and increased throughput. F2.1.3.2 Metallisation The conventional metallisation process is based on electroless copper plating. A temporary plating resist is used to define the conductor tracks. Often a "swell and etch" adhesion promotion system is used to increase the adhesion between metal and polymer as well as increase the ability to comply with mechanical stress. A palladium/tin colloidal is typically used as a catalyst for the deposition of copper. With electroless process, the plating can be done on many panels in a batch process. The plating is uniform, and it will conform to the substrate and provide a coplanar surface regardless of the topography or features. Adhesion to the substrate is often measured by a peel testing, where the metal is peeled normal to the substrate .
F8: Overview of different Build Up technologies, with type of dielectrics and minimum feature sizes.
F2.1.4 Examples In the example below, IBM designed [F3] a MCM-L to improve the performance of two four-port SRAMs by reducing the interconnection length. The result was a 25 % performance increase by reducing the processing time from 20 to 15 ns.
This MCM-L incorporates a wire bond die and surface mount capacitors and resistors onto a 27 mm, six-layer laminate substrate. The 262 I/O at the first-level interconnect are reduced to 169 I/O for interface to the system level board, resulting in real estate as well as I/O reductions. The final package required over-moulding for protection of the fragile wires connecting the dies. To include the surface mount devices to be in the over-mould as well, an innovative solution was proposed whereby the pad surface finish was converted to silver palladium and a conductive epoxy was used to attach the discrete components. The design shown in this figure is an example of the potential for significant space saving by sweeping several ASICs into one package. The original system board design required an area of 125 mm x 125 mm to contain five banks of four ASICs each. Rather than growing the system, board size to accommodate more devices currently packaged in 160 I/O plastic quad flat packs, the solution of sweeping four bare die ASICs onto a laminate carrier was used. The 37,5 mm, eight- layer package represents a 10x savings in total system board real estate required, thus allowing up to a 4-to-1 density improvement for the increased ASIC count.
Figure F7. Packaging multiple ASICs in bare die format results in significant real estate savings. The module shown in Figure F4 is a sweep of four 1Mb x 72 SRAM die. The package features lowtemperature flip-chip processing onto Microvia laminate. Die pitch is 225 µm, and the interface to the system board is a full array of 474 I/O eutectic balls on 1,27 mm pitch. The full array allows each die to be tested individually if desired. Advantages of flip-chip are shown here by allowing die to be placed in close proximity to each other. The backside of the silicon is available for heat spreaders if desired.
Figure F8. MCM-L combining flip-chip technology on Microvia substrate.
F2.1.4.1 Matsushita "ALIVH" technology Matsushita has developed an alternative to "conventional" SBU technology called ALIVH (Any Layer Inner Via Hole). The board is based on Aramid (non-woven) epoxy prepregs, forming the dielectric layers. A laser is used to drill the via-holes, which are then filled with conductive paste. A copper foil is laminated, and patterned by etching. The different layers are than stacked on top of each other and laminated together, and the pattern on the outer layers is formed. The ALIVH board allows for via holes from 50 to 200 µm in diameter to be fabricated between any layers. Most importantly, parts can be mounted over the via-holes, since they are filled with electrically conductive paste. This new technology therefore allows increased area for mounting parts and more freedom in the circuit design. The new ALIVH board reduces weighs by a factor of three compared to boards in the older design. In addition, it actually costs ten percent less. This technology is currently in use for mobile phones. The technology allows more than 80 contact pads per cm2.
Figure F9: A schematic drawing of the ALIVH technology from Matsushita. Table F9: The design rules for Matsushita ALIVH technology.
Figure F10 Cross section of an ALIVE circuit board used in the NTT P201 Hyper Digital Phone.
F2.1.4.2 Casio MR-80 radio The Casio radio contains three printed circuit boards. Of primary interest is the flip chip board or multichip module, a photo-via built-up multilayer board with five flip chip die as well as numerous packaged components. The flip chip die include extensive test patterns for a built-in self test (BIST) at wafer level, and the die pads are electroplated with gold. An anisotropic conductive adhesive film is placed onto the substrate. Casio temporarily mounts the die and performs a functional test based on a test pattern stored in ROM. If the test is negative, the faulty die and the conductive adhesive film are peeled off and replaced. Only once the test is positive is the anisotropic conductive adhesive film cured through pressure and heat. Anisotropic conductive adhesive film has long been used for chip-on-glass in LCD driver applications. A bare driver IC is mounted onto the LCD glass panel as a flip chip, whereby a conductive adhesive film (or paste) provides the connection between the die’s gold bumps and the ITO traces on the LCD glass. This application requires an adhesive-based connection, because the temperature sensitivity of the LCD makes soldering impossible. Due to the superior planarity of the glass, and the CTE match between the glass and the silicon die, such connections achieve high yields and high reliability. Organic substrates, on the other hand, are neither planar nor do they match the CTE of the silicon.
Figure 11 The SBU board used in the Casio MR-80 radio
Figure F12. A cross-section of the SBU board and the flip chip die attach used by Casio.
F2.1.4.3 Sony DCR-PC7 Camcorder Inside SONYs Camcorder there is one special CSP-package. This near wall-to-wall CSP package is assembled to both sides of the main board. The technology pushes the board interconnection density to new heights. The board is an eight-layer surface laminar circuit (SLC) supplied by IBM Yasu. Two built-up layers are required on each side of the four-layer core, which contains power, ground and two etched signal layers. Line widths and vias are nominally 75 and 125 microns, respectively. This board supports an attachment pad density of 95 pads per square centimeter. This is astonishingly high and is what can be expected with future near wall-to-wall silicon packaging. This is four times as high as most of today's leading edge boards of conventional manufacture.
Figure F13. The SBU boards used in the Sony DCR-PC7 Camcorder folded out.
Figure F14. A cross section of the SBU board and a BGA component.
2.1.4.4 Processor module from Kongsberg Ericsson Communication The Norwegian company Kongsberg Ericsson Communicatoin ANS has together with Amitech AS developed a processor module using sequential build-up technology. The module, shown in Figure F16, integrates 12 bare dies on a 6-layer MCM-L substrate. Dimensions are 42.5 x 42.5 mm, and the module is terminated with a 314 pin BGA-package with plastic encapsulation. Design rules for the SBU-board are 100 µm conductors, 200 µm pitch, 250 µm pad diameter and 80 µm via. The viaholes are laserdrilled. A schematic drawing of the SBU-board is shown in Figure F17. This module combines several technologies to achieve high-density packaging and a cost-effective solution. A modular design of the total system gives the opportunity to flexible solutions using new technology.
Figure F16. MCM-L module from Kongsberg Ericsson Communication.
Figure F17. Schematic drawing of the SBU-board
with BGA-termination in the Kongsberg F2.1.5 Future Directions of MCM-L MCM-Ls benefit from single-chip module (SCM) advancements such as ultra fine pitch wire bonding on BT resin substrates as well as evolving low-cost, low-melt flip-chip processes. As BGA pitch shrinks, the technology is directly extendable to MCM-Ls as well. Manufacturing of MCM-Ls has begun to proliferate from module shops into card assembly shops. Vertically integrated companies that provide silicon, silicon packaging, and board-level assembly have found the elements required to process MCM-Ls are already available. Clearly, card assemblers have an in-depth knowledge of processing laminate assemblies. And for some, these processes have stretched to encompass chip-scale and micro-BGA packages, and the most advanced assemblers have developed processes for flip-chip, albeit for prototype purposes. Surface mount equipment has the proven capability of placing area array bare die, primarily due to their sophisticated vision systems. Design tools used for schematic and layout of cards can be adapted for use in MCM-L designs as well. Those shops having engineers experienced with complex test development will be able to take advantage of built-in selftest (BIST) and boundary scan test techniques to provide a full turn key MCM-L offering. As the MCM trend continues toward flip-chip integration, the net result will be an increasing number of sources to manufacture these packages, assuring competitive costs. For MCMs, the drive has come from customers, such as telecom, where cell phones must be light and portable and where base stations must fit into closet-size spaces. MCM-L will continue to prevail in new applications, such as automotive, as advancements in materials and processes continue to be realised. As the growing infrastructure drives costs lower, the consumer market will enjoy the benefits of MCM-Ls as well. General Electric and Lockheed Martin have together developed a technology based on flex print. Naked chips are glued face down onto the pre-fabricated flex print. Electrical connections to the chip are made by laser, with a following metallization step and patterning. In total, it ends up with flexible film with three conductor layers. By moulding the chips in a polymer material, a conventional MCM can be made. Connections to the PCB can be made either as a Ball Grid Array (BGA) or by adding a lead frame. F2.1.6.1 Production of MCM flex The first part of the process is actually to make a fine line flex print with two conductor layers. This will often be done by specialised sub-contractors. The polyimide film is typically 25 mm thick and has copper tracks on both sides, with down to 50 mm conductors and 50 mm metallized via holes. The finished flex print is typically delivered in roles or large format panels. There are several manufacturers hat can deliver these circuits today. In the next part of the process, the prefabricated polyimide film is cut and mounted onto aluminium frames, with dimensions similarly to silicon wafers. This makes it possible to utilise standard silicon processing equipment. At this stage the flex-print is easily testable. The silicon components are glued onto the film with a thermosetting adhesive, by the use of a standard pick and place machine. Both ordinary passive and packaged components can be mounted in the same way. The adhesive bonding is a critical process, and parameters like displacement of components before curing, out-gassing, thermal stability, humidity absorption, glass transition temperature and curing must be controlled. After the components are mounted, a laser is used to cut holes in the flex and the adhesive, down to the metallized contact areas of the components. The use of laser means that there is little risk of "under cutting" as the light is reflected once it hits the metallisation. The whole surface, including the edge of the via wholes, is then metallized with a thin barrier layer of titan, with following electroplating of 2 to 6 mm of copper. A photoprocess is done to create the third conductor layer. If needed, more layers can be added. The component side of the module can now be moulded into plastic, or be left without any moulding, as a thin flexible circuit. Advantages with the technique are:
Disadvantages are:
Important properties of thickfilm substrate materials are:
However, no single material will satisfy all these requirements. This means that various types of ceramic are used as thick film substrate materials, with 96 % Al 2O3 (alumina) as the dominant one. Alumina has many good electrical and mechanical properties please refer to Table F10. It has very good dimensional stability.Table F10. Properties of substrate materials for hybrid technology, and other important properties (In: inorganic, Semi: semiconductor, P: plastic)
It is brittle, and this limits the maximum size to 10 - 15 cm. After the material has been sintered, it is not easy to shape it. However, it can easily be cut by breaking after a partial cut is made by a high power laser, or after tracing with a diamond. For small circuits, it is common to print and mount components on many substrates that are produced together and then broken apart in the end, to make a rational production process. Holes through the substrate may also be made by laser, but it is simpler to form the substrate contour and punch holes while the ceramic is pliable, before the sintering. The thermal conductivity of 20 - 30 W/ oC is approximately 100 times better than for organic materials, and the low thermal coefficient of expansion, 6 ppm/oC, is advantageous for the mounting of ceramic components and semiconductor chips. For circuits with very high power dissipation AlN substrates are used today, with 5 times or higher thermal conductivity than Al 2O3. Many properties are similar to those of Al2O3. The thermal coefficient of expansion is somewhat lower, 4.5 ppm/°C. This, and different surface properties, give a need for special printing pastes on AlN, to avoid flaking off during the high temperature processing. BeO has even higher thermal conductivity than AlN. However, its use is limited by the fact that dust and vapour from BeO are very poisonous. High price is also connected to this fact.For high volume products with lower electrical demands, enamel coated metal is used as substrate, to some extent. Big circuits can be made, and we achieve electrical grounding in the substrate. F2.2.1.1 Materials for conductors, resistors, dielectrics Conductors, resistors and dielectric materials are applied in paste form by screen printing and they are transformed/sintered by heating to high temperature, "firing". The pastes have three main ingredients:
The organic, temporary binders are polymers that give control over the printing properties. They decompose and evaporate early in the firing process, together with the solvents. The glass particles melt in the firing process, adhere to the substrate, bind the active particles together and give stability for the circuit. The high firing temperature, typically 800 - 900 °C, see Figure 16, implies very good long term stability and reliability. Figure F16. Typical temperature profile for thick film firing.
F2.2.1.1.1 Conductors The conducting pastes should give:
Normally one conductor paste can not satisfy all these criteria, and it is necessary to make several conductor prints. The most used conductor systems are gold, copper, alloys of palladium/silver, palladium/gold and platinum/gold, with properties shown in Table F10. Noble metal systems are used because the heat treatment takes place at above 800 °C, where other metals are ruined by oxidation. However, gold and platinum are expensive materials, so the material cost is an important factor in the final price of the circuit. Gold is very well suited as basis for bonding, but it is not suitable for soldering. This is because gold is very quickly dissolved in solder metal during the soldering process, and it gives a brittle intermetallic composition with poor reliability properties. Pure silver has a strong tendency for migration, which may cause reliability problems after some time. However, silver/palladium gives little migration, it is excellent for soldering, and is well suited for making contact areas for printed thick film resistors. Therefore, this alloy is the most used as conductor material, although it has lower conductivity than the pure elemental conductors. Silver is also used in alloys with platinum. Copper has high conductivity and low price. However, strong oxidation in air at high temperature makes it necessary that copper must be fired in a neutral nitrogen atmosphere. This process is more complicated and costly and has impeded the use of copper conductors. Nickel is also used to some extent, but it has lower electrical conductivity than the other materials. Typical thickness for the conductors is 5 -10 µm after firing. The sheet resistivity is typically between 2 and 25 mohm/sq, please refer to Table F11. Table F11. Properties of thickfilm conductor systems.
Silver with 1 % platinum (AgPt) has similar leach resistance and migration properties as AgPd, but the electrical conductivity is much higher. Gold – platinum is sometimes used, since has excellent soldering properties. F2.2.1.1.2 Resistors Important properties of thick film resistors are:
The resistor pastes consist of the same three main ingredients as the conductor pastes, but the active elements have lower electrical conductivity. They are most often based on various types of oxides of ruthenium: RuO 2, BaRuO3, Bi2Ru2O7. In addition, oxides of iridium, rhodium and osmium are used. They may be produced with sheet resistance down to approximately 1 ohm/sq, and up to 109 ohm/sq, for a 25 µm thick print. The sheet resistivity is determined by the active material in the paste, the amount of glass matrix mixed in, and the details in the processing. The tolerance in achieved resistance is lowest for the intermediate values of sheet resistivity.We obtain termination of the resistors by printing a conductor underneath or on top of the ends of the resistor, see Figure F17.
Figure F17. Thick film resistor with termination. Some typical resistor properties are shown in table F12. Resistance drift lower than 0.5 % under harsh climatic conditions over long periods of time makes thick film hybrid technology attractive for demanding applications. The difference in drift between several resistors on the same substrate is typically 0.1 %. The temperature coefficient of resistance depends on the material, and it is typically in the range +/- 100 - 700 ppm/°C, with variation over a circuit, for resistors printed with the same paste, below +/- 15 ppm/°C. The tolerance in absolute resistance after printing and firing is typically +/- 10 - 20 %, and the relative tolerance between resistors on the same substrate one order of magnitude lower. However, by laser trimming one can achieve tolerances down to approximately 0.5 % absolute, and 0.1 % relative value. Table F12. Typical properties of thick film resistors.
F2.2.1.1.3 Dielectrics Dielectric materials are printed to obtain insulation between various layers of conductors, to produce capacitors, and as passivating cover on top of the whole circuit. For insulation, low capacitance between conductors is desirable and we use materials with low dielectric constant. For capacitors, materials with high dielectric constant are used, to achieve high capacitance with little area consumption. Important properties of dielectric materials:
For insulators:
For capacitors:
For insulation layers, aluminium oxide is the common functional element, together with glass. The glass melts and crystallises during firing at 850 - 950 °C, but it does not melt if heated again. The relative dielectric constant is typically er = 9-10, and breakdown field strength 20 V/µm. The dielectrics for high value capacitors consist of ferroelectric materials with er up to above 1000, similarly to ceramic multilayer capacitors, please refer to Chapter 4. However, the properties of these materials change drastically near the Curie temperature. Barium titanate is used, with additives of strontium, calcium, tin or oxides of zirconium to change the Curie temperature and to reduce the temperature coefficient in the temperature range of use. That gives er = 1000 - 3000 and temperature coefficient up to approximately +/- 5000 ppm/°C. For small capacitors the pastes of magnesium titanate, zinc titanate, titanium oxide, and calcium titanate are used, with e r = 12 - 160, and temperature coefficient +/- 200 ppm/°C.Table F13. Typical properties of printed and discrete capacitors.
Capacitors are not suitable for laser trimming. That, in addition to the above mentioned disadvantages, is the reason why printed capacitors are used only in small values and for uncritical purposes (de-coupling capacitors, etc.). Some properties of printed and discrete capacitors are compared in Table F13. Pastes for the protection layer on top of thick film circuits are composed such that they may be fired at lower temperature, approximately 500 °C, and affect the previously printed layers as little as possible.
F2.2.1.2 Production process The layout of the circuit is made by CAD tools, photo plotting or laser plotting, analogous to the ones used for layout of multilayer PCBs. Photographic films are produced for the pattern of each layer. From these films, screens for screen printing are produced, using a photolithographic process. When a print has been made, the circuit is dried in an in-line furnace at typically 100 - 150 °C. Then the firing is done in a different furnace at 700 - 1000 °C. The process is repeated for each layer, but all resistor layers are fired in the same process step, after the conductor-layers are finished. To achieve good reproducibility for resistors the temperature profile, the top temperature and the time have to be very precisely controlled, maximum deviation in temperature is below 1 °C. The smallest conductor width that can be achieved with ordinary printing technique is approximately 100 µm. (Using an extra photolithography and etch step this may be reduced to 50 µm.) It is possible to make conducting contact between the topside and the bottom side of the substrate by printing through holes in the substrate. This is done by sucking the paste through the hole by use of vacuum on the bottom side of the substrate while the printing on the topside is done. To achieve reliable contact the substrate is then turned around and the paste is printed again from the other side in combination with the vacuum. It is common to have all the conductors and discrete, surface mounted components on one side and the resistors on the other for easy laser trimming. Figure F18 shows the typical process flow for a simple circuit with two conductor layers and one resistor layer. Dielectrics are normally printed twice to avoid pinholes that may cause short circuit faults through the insulating dielectric. Figure F18. Process flow for production of thick film circuits. Testing is normally done on the substrates before component mounting, as well as on the completed circuits with the components mounted. Test probe-cards, as shown in Figure F19, are used for the contacting. During the testing the resistors are adjusted by laser trimming (previously sandblasting). It is done by a powerful pulsed YAG-laser automatically focused on one spot of the resistor, evaporating the resistor material, while the resistance value is measured. The laser focus is moved and it removes material along a track, until the resistance value is inside the desired tolerance. The resistance will always increase by the trimming; therefore, the resistance after printing is made 20 - 30 % lower than the desired end value. Three normal trim geometries are shown in Figure F20. With an L- cut the coarse trimming is done with a track perpendicular to the resistor length, and the fine trimming to accurate value is done by the track along the direction of the current. Digital trimming gives the best stability and noise properties but occupies more substrate area.
Figure F19. Probe card for testing of thin and thick film MCMs.
Figure F20. Laser trim cut forms. a): L-cut, the most common, b): Top hat plunge cut, c): Digital trimming, which is most used for high precision resistors.
Figure F21. Laser trimmer for thickfilm hybrid circuits, ESI Model 44. Alternatively active functional trimming may be performed. Then one measures a circuit function (the frequency of an oscillator, the amplification of an amplifier, etc.), and the value for the critical resistor is trimmed until the correct value of the measured parameter is achieved. After completing the trimming of a resistor, the X - Y table on which the circuit is placed is automatically moved and the next resistor is trimmed. A laser trimmer is shown in Figure F21. F2.2.1.3 Component mounting, encapsulation Soldered, encapsulated ICs, as well as wire bonded naked chips, are used on thick film hybrids. SMD passive components are soldered by using solder paste and reflow soldering, or they are glued with electrically conductive adhesive. Reflow soldering is done either with a hot gas convection belt furnace, an IR. (infrared) furnace or vapour phase furnace. The process for "chip-and-wire" mounting and for soldered hybrid circuits is shown in Figure F22. Normally, soldered SMDs are not used on circuits together with wire bonded chip-on board, because of the danger of contamination from the solder process. This may make the surface unsuitable for wire bonding and/or give poor long-term reliability. Conformal coating is an extra protection by an organic material over the components and substrate, for example by using Parylene. Conformal means a coating covering all surfaces. It gives mechanical and environmental protection and binds loose particles. The hybrid circuits may be used non-encapsulated or they may be mounted in metal- or ceramic flat-pack packages. Circuits with naked ICs are encapsulated hermetically or the naked chips may be protected by drops of epoxy ("glob top" encapsulation).
Figure F22. Process flow for mounting thick film hybrid circuits based on a) Bare-die, b)Soldering of packaged components.
F2.2.1.4 Alterations Pacific Microelectronics Corporation has developed a "Transfer Tape Dielectric". This circumvents the problem with pin-holes in the dielectrics which are common for ordinary printed dielectrics. With this technique, there is only need for one layer of dielectric between each conductor layer, whereas ordinary thick film techniques requires at least two layers. Since the first conductor layer only can be fired a certain number of times, this increases the possible number of conductor layers on a thick film substrate. Since the number of process steps is reduced, the potential cost of the circuit is reduced. F2.2.1.5 Design rules Some of the general design guidelines for PCBs, given in Chapter 6, also apply for hybrid circuits. The smallest conductor widths and distances are normally 0.2 mm. The demands for low voltage drop in high current circuits may cause the need for wider conductors. The smallest length and width for resistors are 0.5 - 1 mm. The ratio between length and width should be between 0.1 and 10. For resistors that dissipates much power the resistor area should be increased such that the dissipation is maximum 100 mW/mm2. An efficient ground plane is achieved by metallizing the complete underside of the substrate. F2.2.2 High Temperature Cofired Ceramics LTCC High-temperature multilayer ceramic technology has been used for many years for ceramic capacitors and for IC packages. For packages and multichip modules, Al 2O3 and AlN (BeO and SiC to a smaller extent) are used. For multichip modules, alumina is the most used material, with 92 - 96 % Al2O3 content. The structure consists of many layers of ceramic, with metallisation between the layers, and via holes through the layers for electrical contact. The best known application of large modules with many layers of ceramic is IBM´s pioneering product "Thermal Conduction Module" (TCM) for mainframe computers, already in 1983. The module had 33 layers, and 133 silicon chips were mounted by flip chip soldering. Since then, mainframe computer manufacturers have used analogous technology, based on materials with even better thermal performance.
Figure F23. Production process for multilayer ceramic, schematically.
F2.2.2.1 Fabrication The fabrication of multilayer ceramic modules by "tape casting" is shown schematically in Figure F23. The non-sintered, pliable ceramic consists of alumina powder, organic binders and solvents. The material is spread from a container down on a transport carrier underneath. The ceramic "tape" ("green sheet"), is given the appropriate thickness on the transport carrier by passing underneath a "doctor blade" in a precisely controlled distance. The tape is cut to correct size, and holes and component cavities are punched out with a numerically controlled punching tool or with a permanent, product specific punching tool for high production volume of a given product. Metallisation of the via holes and fabrication of conductors is done by screen printing of tungsten (or molybdenum). These are the only metals that can withstand the high process temperature during the subsequent sintering process. All layers are laminated together under hydrostatic (or uni-axial) pressure at elevated temperature (500 – 600 °C), to evaporate the binder and solvent. Then the whole structure is sintered at 1370 - 1650 °C, 30 - 50 hours, in hydrogen atmosphere. For small circuits, many modules are made on one substrate, and the individual circuits can be parted by breaking the substrate at the end of the process. Then the external contacts are brazed to the substrate and finally gold may be plated on the surface with nickel as diffusion barrier on top of the tungsten. The plating is preferably done electrolytically to achieve sufficient thickness and good conductivity, if one can make electrical contact to all parts of the conductor pattern. Otherwise, chemical plating is used. During the process, the ceramic shrinks approximately 18 % linearly. This has to be taken into consideration during the design of the circuit, both sideways and in thickness (which affects the characteristic impedance). Normally the designer will operate in correct dimensions and the producer will scale the CAD information up by the necessary amount for production of printing screens and punching tools. The shrinkage is material- and process dependent, so the finished circuits typically have linear dimensional tolerances 0.5 - 1 %. F2.2.2.2 Properties Some electrical, physical and mechanical properties are shown in Table F14. Black ceramic is used the most, the white material has somewhat higher purity and better properties at high frequencies, but it is transparent in a range of light wavelengths and is more expensive.
The minimum conductor widths and conductor distances are typically 0.15 - 0.2 mm. Minimum diameter of via holes is typically 0.1 - 0.2 mm. Extended ground planes are made as grids of printed lines rather than continuous, due to the dissimilar thermal expansion of metal and ceramic. The typical thickness of the printed W conductor layer is 15 µm. The electrolytically plated Au on the surface is 2 µm or more, with a 2 µm Ni barrier/adhesion layer between the Au and W. Among the advantages of high temperature multilayer ceramic are the following:
Among the disadvantages are the following:
Table F14. Properties of alumina-based high-temperature multilayer ceramic.
F2.2.3 Low Temperature Cofired Ceramics LTCC DuPont, IBM and others have introduced multilayer ceramic based on glass compositions similar to those used in thick film dielectrics, instead of alumina. The fabrication is made in a process similar to that used for high temperature ceramic. The advantage of the low temperature technology is primarily that the sintering takes place at around 850 °C, 15 min., normally in air atmosphere (after a burnout at 350 °C to remove the organic binders and solvents). The effect of this is that the metal systems used in ordinary thickfilm technology are suitable for inner layers, with much better electrical conductivity than tungsten. Thick film firing furnaces may be used for the process. Resistors may also be printed in the inner layers. Materials in the substrate are mullite, corderite, lead borosilicate glass and others. DuPont, one of those making the base materials, is promoting the technology among the thick film producers. The tape casting of the tape materials is done by DuPont and the user buys the tape mounted on a Mylar foil that is removed before the punching and printing. In Europe some three producers make custom designed low temperature ceramic circuits (1992), and many companies are testing out the technology. Several producers in the USA and Japan are making low temperature multilayer ceramic circuits, primarily for internal use. Table F15. Properties of low-temperature multilayer ceramic.
Table F16. Resistor Performance - Resistance and TCR.
Table F17. Physical Properties.
Many properties are similar to those of the high temperature system, but the thermal conductivity is about 5 times lower for the low temperature materials. The shrinkage is only approximately 12 %. The materials are more brittle than alumina, and they must be handled with caution. Some parameters are given in Table F17. Typical conductors minimum width and separation are 0.15 - 0.2 mm, diameter of the via hole 0.15 - 0.2 mm, and distance between via holes 0.25 - 0.4 mm. The DuPont tape is made in two standard thicknesses: 90 and 250 µm (after sintering). The surface roughness is approximately 1 µm, lot-to-lot variation of the shrinkage: 0.2 %. The relative dielectric constant er = 7.5 - 8.0 (but materials with lower er are available), tan d = 0.2 - 1 %. Thermal conductivity K = 2 W/m °C. Buried, silver based conductors have quite good migration properties, and the resistors have properties similar to those of thick film resistors. Circuits with 20 layers of ceramic have been demonstrated, the potential is said to be over 40.Some advantages compared to high temperature multilayer ceramic technology are:
Disadvantages:
A "transfer tape" version is also available, which is fired for each layer. F2.3 MCM D F2.3.1 Thin Film Technology Thin film hybrid technology that has been in use since the 1960´s, with one layer of conductor, one layer of resistor and an inorganic dielectric. Thin film circuits consist of conductor layers, resistor layers and dielectric layers, similarly to thick film circuits. However, the conductor thickness is normally 1 µm or less, an order of magnitude less than for thick film. Processes from the semiconductor industry are used for deposition of conductors and dielectrics and for the definition of patterns. That gives a much higher circuit density than in thick film. The substrate materials that are used the most are 99.6 % alumina and glass. The fine conductor line dimensions require a smooth and uniform surface, so the alumina substrates are polished. The purer quality alumina, used in thin film circuits has lower tan d than the substrates used in thick film technology. This is particularly important for high frequency use.The metal that is used for most for thin film conductors are gold. Gold is chemically stable, it has high electrical conductivity and good bondability. However, as previously mentioned, gold diffuses very rapidly into many other metals. Together with gold special, elements are used as diffusion barriers, and in addition as adhesion layers, because gold has poor adhesion to non-metallic materials. Nickel is suitable for diffusion barrier, a nickel/chromium alloy improves the adhesion, and it is also suitable as resistor material, see below. The much used Au - NiCr system is deposited by vacuum evaporation or by sputtering. Gold may also be electrolytically plated. This is particularly important for microwave circuits, where a 5 - 10 µm thick layer gives low conductor resistance, reducing the high frequency loss. Various materials are used for dielectric depending on whether one wants to make capacitors, multilayer insulation or passivation. For passivation, SiN 3 is well suited. SiO2 is used much for insulation between conductor layers, because it has low dielectric constant (er = 4), and high breakdown field strength (106 V/cm). Both are produced by chemical vapour-phase deposition. For capacitor dielectric SiO2, Al2O3, Ta2O5 are used. They are produced by vacuum evaporation, chemical deposition, or anodic oxidation.Resistors are made, as mentioned, from NiCr, as well as Ta 2N, by vacuum evaporation or by sputtering.While we can achieve over 6 decades of variation in sheet resistivity in thickfilm hybrid technology, the range we achieve with practical thickness in thin film technology is only between approximately 10 and 1000 ohm/sq. Some properties are shown in Table F18. Table F18. Properties of thin film resistors.
F2.3.1.1 Production process Figure F25 shows the process steps for a thin film circuit, with one conductor layer and one resistor layer. In the first step, the resistor layer is deposited all over the substrate. If the circuits are small, many circuits are made on the same substrate, and they are separated at the end of the production process. First a diffusion barrier (also improves the adhesion) is deposited and then the conductor metal. This is preferably done in the same vacuum chamber, in order to have a clean surface and good adhesion. These standard processes require special equipment and clean room facilities. Minor thin film circuit producer companies will normally buy the substrates, which are processed to this stage. Conductor and resistor geometries are defined by photolithography and etching. A few drops of photoresist are deposited and spread by the centrifugal force when the substrate is rotated on a spinning disk. The conductor pattern for the circuit is defined by exposing the resist through a photo mask, development and curing. Then the gold is removed by etching where it is not wanted. A solution of potassium iodide solution may be used for etching the gold, without dissolving the NiCr layer. If the need exists for conductor widths less than 2-3 µm, the etching is done by reactive ion etching, which etches fast vertically, but more slowly horizontally, and thus reducing the under-etching. A new step of photo-processing is done to define the pattern of the resistors, and the diffusion barrier and the resistor films are etched where they are to be removed, for example with nitric acid. (Where the circuit has conductor pattern, there is still the resistor layer underneath the conductor material, see Figure F25.)
Finally, the circuit is cured in air at 250 - 350 °C for some hours, to make a passivating layer of chromium-oxide to protect and stabilise the resistors.
F2.3.1.2 Thin film components A type of "components" that is very suitable for being made by thin film technology is precision R/C networks. They are also available as off-the-shelf components for mounting on other thin- or thick film substrates. Diodes and transistors can also be fabricated. Large thin film diodes made from Cu 2S/CdS hetero-junctions give low price solar cells, and thin film transistors have been under development for 10 - 15 years. A matrix of thin film transistors is of great interest for the control of big LCD screens for flat televisions, etc. The structure is similar to Si -MOS transistors, see Figure F27. CdSe as well as Si/H are used as the semiconducting material.
Figure F27. Thin film transistors, structure. F2.3.1.3 The complete thin film circuit When the thin film substrate has been completely processed, resistors may be laser trimmed like in the case of thick film circuits. After this, components will be mounted on the substrate. Integrated circuits are normally mounted in the form of naked chips that are glued on to the substrate and wire bonded. Discrete resistors and capacitors are normally mounted with conductive adhesives for electrical and mechanical contact and not soldered. In most cases, the complete circuit will be mounted in a hermetic package that is made of metal, or in some cases of ceramic. Terminal points on the substrate will be connected to the leads of the package by wire bonding. A welded or soldered metal lid on the package ensures hermeticity and good reliability. F2.3.1.4 Multilayer thin film, multichip modules This is an extension of conventional thin film technology, but with many conductor layers, that makes it possible to achieve a very high circuit density. We may also achieve controlled characteristic impedance and good high frequency properties. The normal substrates are either 99.6 % alumina or silicon wafers. Figure F28 shows a cross section. The dielectric most often used is polyimide or benzocyclobutene. The organic dielectrics are deposited in a similar way as the photoresist described earlier to a thickness of approximately 10 µm. Some of these materials are photo immagible, which means that they can be patterned without the use of an additional photoresist. The dielectric constant as well as the dielectric loss for these materials is low which means that good high frequency performance may be obtained. Also non organic materials like silicon oxide and silicon nitride are used for dielectrics. These materials are deposited by chemical vapour deposition or sputtering. These materials will typically be deposited in a thickness of the order of 1 mm. The dielectric constant is significantly higher than for the organic materials. On the other hand, these dielectrics give a hermetically sealing of the metal tracks.Aluminium (Al), copper (Cu), and gold (Au) are most commonly used as conductor metals. IC process technology makes it possible to achieve a minimum conductor width/distance of 25 µm or less, i.e. a higher conductor density than any other substrate technology (except full wafer scale integration). AT&T has been a pioneer in this technology. Over 100 companies and research labs had this technology under development / production in 1992 and it will be a mainstream technology for high performance systems during the coming years. One high performance product employing the technology is the mainframe computer VAX 9000, of Digital Equipment Corporation. Silicon substrates are used and the IC chips are mounted as TAB-components.
Figure F28. AT&T´s structure for multilayer thin film.
A typical process is as follows:
Some design rules for Raychem´s "High density interconnect" (HDI) technology are shown in Figure F30. All the way up to 10 GHz the losses in the conductor dominate, the dielectric loss is negligible. However both the dielectric constant as well as the dielectric loss depends on the moisture absorption in the polyimide: er = 3.4 (dry) and 4.5 (maximum moisture content, 3.5 %). A lot of work is going on to develop new types of polyimide and alternative materials that are less hygroscopic.
Figure F30. Elements of the design rules for Raychem´s HDI technology. For ICs with high power dissipation it is possible to make a "thermal well", by mounting the chip directly on the substrate, without the polyimide which acts as a large thermal resistance. This technique is used in the VAX 9000 computer, where ECL technology gives high power dissipation. However, the result is a reduced area for signal routing. Some advantages of multilayer thin film with Si substrates:
Some disadvantages:
F2.3.2 Alternative techniques (substrates) Micro Module Systems has developed a thin film technique based on aluminium substrates. Polyimide is used as dielectric, and copper is used for metallisation in the inner layers, whereas gold is used at the outer layer to allow ordinary wire bonding. The minimum pitch is 50 mm, which gives 200 conductors per centimetre. The via-holes are formed by plasma etching, where all the holes are etched in one step, which gives potentially low cost. The components (passive, bare dies or packaged chips) are glued to the substrate with a special glue. The large miss-match in thermal expansion between the components and the aluminium means that large QFP components can not be used. Flip chip technique is not possible either due to the miss-match. The metal substrate can be used as a ground plane.F2.4 IBM’s Thin-film on ceramic IBM offers thin film MCMs on glass ceramic [F4], which address the needs of the high-end, high-performance semiconductor applications, represent an advance over the standard alumina substrates. The MCM is based on a multilayer glass ceramic, known as corderite (borosilicate glass), onto which a polyimide based thin film structure is added. The two parts are described below. F2.4.1 Properties of IBM’s glass ceramic multilayerIBM is using a corderite glass multilayer ceramic (MLC) with copper circuits capable of accommodating off-chip I/O up to 5000 and off-package I/O count of more than 1600. The material has a matched thermal coefficient of expansion with silicon, addressing the needs of those high-end applications requiring large die sizes to integrate complex function. The size of a typical high-performance MPU is 18 mm square or larger [F5], making it important to find materials with a lower thermal coefficient of expansion (TCE) to match that of silicon. The glass ceramic package accommodates die sizes up to 30 mm on edge without chip-to-package reliability concerns. The copper conductors and low dielectric constant of the glass ceramic deliver improved electrical performance, a typical characteristic impedance of 50 ohms and high dimensional stability. Higher processor speed requirements have led to a search for packages with lower resistance wiring and lower dielectric constant. The controlled collapse chip connection (C4) of flip-chip die in this size range needs improved fatigue life as MPU field conditions demand higher numbers of on/off cycles, higher operating temperatures and very high numbers of mini-cycles (rest-mode) [F6]. Furthermore, the stress in the silicon itself grows proportionally to the TCE of the chip carrier as large die are attached and underfilled to the carrier [F7]. F19. The key features of the multilayer ceramic substrate.
Table F20. Dimensional features of the ceramic substrate.
F2.4.2 Properties of IBM’s multilayer thin film In addition to supporting significantly higher speed for critical nets, the thin film-based G5 MCM enables higher chip I/O density and higher net density (lines/cm2). In addition, higher simultaneous switching activity (with lower delta-I noise despite higher speed switching and greater delta-I current), and a lower signal-signal coupled noise is obtained. The fine pitch of the thin film wiring (18 µm lines on a 45 µm pitch) enables theG5 MCM to support chips such as the SC, which require 1250 signal I/Os. The fine pitch thin film wiring was also essential to positioning large (17+ mm) chips on a pitch of only 22 mm. This extremely tight placement of chips also contributed to minimising critical net path lengths, essential to meeting the 4-ns system cycle time objective. The high performance, along with good cost/performance of the G5 module and system, would not have been achievable without the use of the multilevel, fine-featured thin film structure. The dielectric material is polyimide and via holes are made by laser ablation. The first metallized thin film layer, M0, is used for capture pad and voltage mesh. This layer contains capture pads, which overlay the copper vias in the glass ceramic. The capture pad is the electrical interface between ceramic and thin films (Figure F31).
The mesh in the M0 thin film structure provides uniform voltage distribution. The next metal level, M1, is another voltage mesh. The first wiring level, M2, follows. This is the X wiring level of the X/Y plane pair. It consists of 18-micron wide Cu lines that are 5 microns thick on a 45-micron pitch. The Y level, M3, has the same design ground-rules as the X layer. The two wiring layers run perpendicular to one another to reduce coupling. Within this single plane pair are 212 meters of signal wiring. Following the X/Y plane pair is the M4 level, which is a ground mesh. The three voltage planes together provide a low inductance path between the chips and the high-performance de-coupling capacitors. This reduce the system level delta-I noise, even though there is a larger number of simultaneously switching drivers switching at higher speeds than in the earlier G4 system. The uppermost thin film layer, M5, provides the structures needed for chip-to-thin-film connectivity and reworkability as well as top surface line structures, which provide signal net repairability for both thin film and ceramic nets. Net repairability is accomplished by laser line deletion and line reconnection to form alternate net paths. This technology enables the production of highly complex wiring in high yield. The metallization of the M5, unlike the copper only of the other layers, consists of chrome, copper, nickel, and gold. This particular structure is needed to create a good intermetallic connection between thin film pads and the lead/tin solder I/O of the chip, also known as the chip C4. Between every thin film metal layer is a 6- to10-micron layer of low dielectric (3.2), low TCE polyimide, through which approximately 55,000 vias are created per layer by laser ablation of the polyimide through a patterned mask. When ultimately metallized, these small vias (on the order of 20 microns in diameter) provide reliable layer-to-layer thin film connectivity (Figure 3). Thin film metallization is accomplished by sputtering metal onto the surface, followed by photo definition of the pattern and then pattern creation through either sub-etch or plate-up techniques. F2.4.3 IBM’s G5 MCMIn May of 1998, the S/390 G5 Parallel Enterprise Server was announced by IBM as the newest and most powerful member of IBM’s mainframe family. Originally anticipated to offer more than 900 million instructions per second (MIPS) when configured as a "10+2" system, the S/390 G5 actually delivers a 15% increase in performance, making it the first commercially available mainframe in the 1000+ MIPS range. This performance is closely connected to the glass ceramic/thin film packaging. The result is the G5 multichip module (MCM), which, as the heart of the S/390 G5 system, offers both outstanding processing speed and very high reliability. The G5 MCM is a 127,5 mm glass ceramic substrate consisting of 75 layers of ceramic, with six levels of thin films. This structure supports a system design with 12 CPUs and a total of 29 chips operating at a 4-ns system cycle time. There are a total of 12.000 nets in this MCM, with a total wiring length of approximately 600 meters. A picture of the MCM is shown under, where the TSM side of the S/390 G5 MCM after thin film completion are seen. The 29 chip sites and the de-coupling capacitor sites between the chip sites are clearly visible. The one site in the centre of the top row is used for thin film process control. Two additional thin film layers are built on the bottom surface of the MCM to support a high-density pin grid array. For both thin films and glass ceramic, this package represents the greatest number of layers and wiring length used in any MCM package announced to date by IBM. Table F22 shows a comparison of thin film packages used in various IBM systems.
*Redistribution wiring only A large portion of the glass ceramic layers that comprise the G5 MCM are represented by 17 X/Y signal wiring plane pairs. The thin film structure supports an additional high density X/Y plane pair. This one thin film plane pair—as a consequence of its fine pitch wiring—is the equivalent of 10 ceramic plane pairs. By leveraging the thin film wiring density to reduce ceramic layers, performance is enhanced and package thickness and cost are reduced. The thin film structure not only provides signal wiring capability, but also provides structures for several other critical functions:
On the BSM 4224 thin film I/Os are symmetrically arranged into four quadrants, each with an equal number of pins (Figure 5). Gold pins are then gold/tin brazed to the I/O pad. These pins then provide the connection to the S/390 G5 system board.
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