This chapter covers the different varieties of multichip modules. Chapter 1.1 to 1.7 is an introduction to the subject and is intended for those who want an overview of the technology. Part 2 cover each of the substrate technologies in more detail. The attachment and encapsulation technologies are covered in other parts of this guideline. Most of the material in the chapters; 2.2.1.1 to 2.2.1.5, 2.2.2.1 to 2.2.2.5 and 2.2.3.1 to 2.2.3.5 is with the authors permission taken from the book "Electronic Components, Packaging and Production" [1] by Leif Halbo and Per Øhlckers.

A Multi Chip Modules, abbreviated "MCM", is described as a package combining multiple ICs into a single system-level unit. The resulting module is capable of handling an entire function. An MCM can in many ways be looked upon as a single component containing several components connected to do some function. The components are normally mounted un-encapsulated on a substrate where the bare dies are connected to the surface by wire bonding, tape bonding or flip-chip. The module is then personated by some kind of plastic moulding. The module is then mounted on the PCB in the same way as any other QFP or BGA component.

MCMs offer an astounding variety of advantages instead of mounting packaged components directly on the PCB:

There are several aspects to consider when choosing the right technology for a multi chip technology. Below follows a discussion of some of them.

MCM designs are very practical when integration of mixed silicon technology is required. Silicon germanium is an enabler of high-frequency applications, such as global positioning systems and satellite systems operating in the GHz frequency range. For these designs, MCMs provide the integration required plus the benefit of a smaller overall package combined with performance. The best argument for using MCMs over ASICs, though, is time-to-market. MCMs can enable functional products to enter the marketplace several times faster than comparable ASIC designs. This is significant for prototype designs or products for competitive low-cost demand.

For products with longer life cycles, the total cost scenario must be analysed. Assembly yield considerations become significant for high-volume applications. Although MCMs have a low up-front cost compared with ASICs, factors such as die yield and assembly yield can keep costs high over the life of the product. The advantage of ASICs in this scenario would be the opportunity to spread the up-front engineering cost over the piece price and leverage the resulting high yield. In the case of an existing product where mature die is being utilised and product shrink is required, an MCM might make more sense. In many cases, the optimum solution might dictate the use of MCM technology to achieve acceptance, followed by an ASIC to support production volumes. Integration of silicon sometimes enables incorporating ASICs onto an MCM to combine memory and clock drivers to overcome the challenges of the speed limitations at the board level.

The electrical performance of a package is mainly determined by the geometries and materials used in the package. If high frequency properties are important, a technology must be chosen that offers dielectrics with both low dielectric constant and low dielectric loss. The metal system must have high specific conductivity to minimise the conduction losses. At high frequency, the skin effect means that only the surface of the conductor contributes to the conduction. To obtain well-controlled characteristic impedance the technology must allow precisely defined conductor edges. This means that substrate and the added dielectric layers must have a smooth surface. Water absorption in organic dielectrics will cause a significant change in dielectric constant, changing the impedance of a line. In a harsh environment, this might imply that a circuit with organic dielectric has to be packaged in a hermetic package.

For some applications, the thermal properties are important. The first way to improve the thermal properties is to choose a substrate with a good thermal conductivity, like certain ceramic materials (beryllium oxide or silicon nitride), silicon or metal based substrates. If the substrate itself is not able to cope with the power, alternative heat paths have to be found. This can be to attach the chips to some type of heat sinks, and use natural or forced convection priciples to bring the die-temperature to the specified level.

If miniaturisation is the main goal, parameters like line width, line spacing and via-hole dimensions become very important. The type of electrical connection between the die and the substrate will also play a role, as both wire bonding and TAB needs certain spacing along the chip for the connection. Flip Chip technology on the other hand requires no extra area.

In many applications, cost is the main constraint. When discussing cost it is very important to consider the production volume, as some technologies will have a substantial "start up" cost. The way the total circuit is divided (or partitioned) into different sub modules will be very important for the total cost. Production yield and reparability will also have a mayor influence on the cost, as well as the problems associated with known good die (KGD).

The cost can be divided into substrate cost, which covers both the mechanical carrier as well as the conductor pattern. Both material cost and processing cost must be considered. The choice of encapsulation also has a big influence on the cost, and must be considered in connection with the environment in which the circuit is going to operate. Another important factor to consider is the test issue. This must be taken into account right from the module design.

The substrate forms the basis of the MCM and is the technology, which gets most attention. There exist an overwhelming amount of different technologies, each with its own set of advantages and disadvantages. To classify the different technologies, a division in the groups is often used based on the fabrication technique. The three techniques are Lamination, Deposition and Ceramic sintering.

Lamination based MCM’s is today a very promising technology for many applications. Although greatly modified in some respects the MCM-L technologies is much based on the traditional printed circuit board technique where several layers of conductors and organic dielectrics are laminated together with pressure and heat cured. Several of the MCM-L technologies today are actually very fine-line printed circuit boards.

Since these technologies have potential for low cost and high density, numerous variations of the technology are developed.

Advantages

Disadvantages

	Low tooling cost implies acceptable prices, also for low volumes.
	Relative low coefficient of thermal expansion that is compatible with silicon.
	Medium to high thermal conductivity allows a simpler thermal design.

F1.4.2.2 High Temperature Cofired Ceramic (HTCC)

As the name implies in this technology all the layers is fired at the same time under high temperature (approx. 1600⁰C). This is probably one of the most used ceramic technology and its main use today is in single chip packaging where high I/O IC’s is mounted in a Pin Grid Array (PGA) or a Ball Grid Array (BGA). There are not many metals that survive 1600 ⁰C firing so the chosen conductor material is Tungsten. This is however, a metal with relative low electrical conductivity, and therefore not too well suited for the inter-chip interconnect in MCMs. The high shrinkage during firing also makes small vias difficult.

The conductor patterns is added to a dielectric tape by screen printing after the via-holes are punched in the tape. The via-holes are also filled with conductive paste in the printing process. The layers are then stacked up, laminated under pressure and temperature, and at last fired in an oven at 1600 ⁰C.

Advantages

Disadvantages

F1.4.2.3 Low Temperature Cofired Ceramic (LTCC)

As the name implies that this is the same process as the HTCC except that in this technology all the layers is fired at the same time under a relatively low temperature (approx. 800 ⁰C). The low firing temperature enables the use of precious metals in the conducting layers. The dielectric has somewhat lower dielectric constant.

Advantages

Disadvantages

	Narrow lines possible.
	Low dielectric loss tangent (» 0.0001)
	Resistors and small capacitors can be integrated in the wiring
	Trimming of resistors is possible
	Good - very good thermal performance, depending on the substrate (l » 30-200 W/mK)

F1.4.3.2 Silicon thin film

Silicon thin film technology is a simpler version of the VLSI process, where conducting layers of aluminium, separated by layers of silicon dioxide is placed on top of a silicon wafer. Often older process lines designed for semiconductor fabrication is converted to MCM lines. Often one or two layers of polymer thin film is deposited on the top aluminium layer. The low thickness of the silicon dioxide compensates for the low thermal conductivity.

Advantages

Disadvantages

F1.4.3.3 Polymer thin film

Polymer thin film a technology where thin (<15um) polymer dielectric films is deposited on a stable base substrate such as silicon or alumina. Thin (2-5um) conductor films, usually copper, is then deposited and processed photolithographically. The lower dielectric constant of the polymers (Polyimide, BCB, etc) together with the 10-15um thick dielectric make 50 Ohm lines more practical.

Advantages

Disadvantages

Wire bonding is currently the dominant chip to substrate connection method. The chip is attached to the substrate with the bonding pads facing away from the substrate. Connecting wires (bond wires) made of gold or aluminium are then attached by welding on the chip pads, pulled to the substrate pads and again attached by welding. Details can be found in the wire-bond guide.

Advantages

Disadvantages

Tape Automated Bonding is a technique where the chip is attached to a polyimide tape prepared with copper conductors. This attachment called the inner lead bond is normally done at the wafer "Fab". The copper wires are connected to the pre-bumped chips by thermocompression bonding, typically all in one go (gang bonding). This, however, may cause cracks in the chip passivation and sometimes one and one lead is connected at the time to allow better control of the bonding. The chips are normally distributed on rolls.

In the assembly plant, the tape is cut in such way that the outer part of the conductors (leads) is exposed. The chip/film assembly is then aligned and soldered or glued to the substrate using conductive adhesive. Normally the cutting and bonding is done in one operation with a tool specially designed for the chip/film assembly. In some applications, a technique called "flip-TAB" is used. In this case, the chips are faced towards the substrate before bonding. This allows much shorter wires and therefore increased high-frequency properties as well as increased packaging density.

Because of the high tooling investments, this technique is mostly used in very high volume products such as watches and LCDs.

Advantages

Disadvantages

	Very high IO count possible by covering the whole chip area with pads
	Ultimately cheap when infrastructure is settled
	Self alignment under reflow ease registration requirements
	Ideal for high frequency applications due to very low contact inductance
	Work with modern SMT lines equipped for Flip-Chip

When using bare dies on a substrate the chips must normally be protected from the environment. The most common dangers for the bare chips are mechanical damage and moisture related corrosion. A flip chip with a proper underfill does not normally require extra encapsulation. A few of the most popular techniques is described below.

	Simple and easy adaptable
	Almost no tooling cost
	Low thermal stress under production
	Well suited for BGA type packages

	Fast, good for high volume production
	Cheap materials

	Guaranteed hermeticity
	Medium - low thermal resistance, depending on the substrate
	Good shielding properties

The strategy of testing of multi chip modules must be considered carefully before starting the design of a multi chip module. Because of the dense packaging, placement of test probes can be difficult.

IEEE 1149.1 "Test Access Port and Boundary Scan Architecture" is a scan method for printed circuit boards. The memory elements which make the scan chain, are placed in the bonding pads of the integrated circuits (IC). Each IC also contains a small controller with which the user may control what to test. The intended use of B-Scan was interconnect test where a test pattern is imposed on the outputs of one IC, and the response is received at the input of another IC. The concept is also useful for other features like checking correct placement, starting and receiving results from component self-test, etc.

Advantages

Disadvantages

	May be the only way to test embedded RAM, ROM, etc.
	Runs at system speed

The world of MCM’s sports more acronyms than most other technology. Below is a table of the most used acronyms together with a short explanation.