Print the references in .pdf format by clicking the link Print References.

D4.1 Recommended Reading

J. H. Lau and Y.-H. Pao, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, McGraw-Hill, 1997.

K Boustedt, P.-E. Tegehall, "The Chip Scale Packaging Task Force - Users and Manufacturers Working Together", Proceedings Second International Conference on Chip Scale Packaging (CHIPCON 97), Sunnyvale, CA, February 20-21, 1997, pp. 167-170.

P.-E. Tegehall, "A Test strategy to verify the Reliability of Chip-Scale Packages", Chip Scale Review, Nov 1998, pp. 73-81.

D4.2 General References

D1. J-STD-012, Implementation of Flip Chip and Chip Scale Technology, The Institute for Interconnecting and Packaging Electronics Circuits (IPC), January 1996. (http://www.ipc.org)

D2. E, J. Vardaman and T. Goodman, New CSP Developments and Applications, Proc. Second Int. Conf. on Chip Scale Packaging (CHIPCON), pp. 10-13, 1997.

D3. R. T. Crowley, T. Goodman, and E, J. Vardaman, Chip-Size Developments, Report from TechSearch International Inc., Austin, Texas, 1995.

D4. S. Greathouse, Chip Scale Package Solutions – The Pro’s and Cons, Proc. Second Int. Conf. on Chip Scale Packaging (CHIPCON), pp. 1-9, 1997.

D5. MIL-STD-883D, Test Methods and Procedures for Microelectronics, November 1991.

D6. JEDEC Standard No. 22 (Collection of test methods), Joint Electron Device Engineering Council (JEDEC).

D7. T. C. Chung, C. Hilbert, and M. Robertson, Updates on Worldwide Chip Scale Packaging, Proc. Second Int. Conf. on Chip Scale Packaging (CHIPCON), pp. 101-109, 1997.

D8. JEDEC Standard No. 34, Failure-Mechanism-Driven Reliability Qualification of Silicon Devices, Joint Electron Device Engineering Council (JEDEC), March 1993.

D9. G. Murakami, CSP with LOC Technology, Proc. ISHM ´96, pp. 594-599, 1996.

D10. Y. Kunitomo, Practical Chip Size Package Realized by Ceramic LGA Substrate and SBB Technology, Proc. SMI, pp.18-25, 1995.

D11. H. Iwasaki, CSP technology and bare chip mount, Proc. ISHM conf. pp. 259-264, 1996.

D12. A. Badihi, A Chip Size Integrated Circuit Package, Proc. Semicon/Europe Tech. Prog., 1996.

D13. T. Chou and J. Lau, A Low-Cost Chip Size Package – NuCSP, Circuit World, Vol. 24, No. 1, pp. 34-38, 1997.

D14. J. Kasai, M. Sato, T. Fujisawa, T. Uno, M. Waki, K. Hayashida, and T Kawahara, Low Cost Chip Scale Package for Memory Products. Proc. SMI, pp. 6-17, 1995.

D15. Y.-G. Kim, B. Ham, S. Choi, and M.-K. Kim, Bottom-leaded Plastic (BLP) Package: A New Design with Enhanced Solder Joint Reliability, Proc. 46th ECTC, pp. 448-452, 1996.

D16. R. Joshi and A. Chen, A New Plastic Chip Carrier (PCC) Package, Proc SMI, pp. 231-235, 1996.

D17. E. Lacap, The Development of the Ultra-Thin Leadless Package (ULTP), Proc. First Pan Pacific Microelectronics Symp., pp. 31-36, 1996.

D18. R. N. Master, R. Jackson, and S. K. Ray, Ceramic Mini-Ball Grid Array Package for High Speed Device, Proc. 45th ECTC, pp. 46-50, 1995.

D19. R. Lanzone, Ceramic CSP: A Low Cost, Adaptive Interconnect, High Density Technology, Proc Second Int. Conf. on Chip Scale Packaging (CHIPCON), pp. 18-41, 1997.

D20. K. Banerji, Devlopment of the Slightly Larger Than IC Carrier (SLICC), Proc NEPCON West, pp.1249-1256, 1994.

D21. Y. Yamaji, H. Juso, Y. Ohara, Y. Matsune, K. Miyata, Y. Sota, A. Narai, T. Kimura, K. Fujita, and M. Kada, Development of Highly Reliable CSP, Proc. 47th ECTC, pp. 1022-1028, 1997.

D22. G. A. Forman, R. A. Fillion, R. F. Kolc, R. J. Wojnarowski, and J. W. Rose, Development of GE’s Plastic Thin-Zero Outline Package (TZOP) Technology, Proc. ECTC, pp. 664-668, 1995.

D23. S. Matsuda, K. Kata, H. Nakajima, and E. Hagimoto, Development of Molded Fine-Pitch Ball Grid Array (FPBGA) using Through-Hole Bonding Process, Proc. 46th ECTC, pp. 727-732, 1996.

D24. S. Tanigawa, K. Igarashi, M. Nagasawa, and N. Yoshio, The Resin Molded Chip Size Package (MCSP), Proc. 17th IEMT Symp., pp. 410-415, 1995.

D25. R. Chanchani, K. Treece, and P. Dressendorfer, mini Ball Grid Array (mBGA) Assembly on MCM-L Boards, Proc. 47th ECTC, pp. 656-663, 1997.

D26. T. DiStefano, The µBGA as a Chip Size Package, Proc. NEPCON West, pp 327-333, 1995.

D27. J. L. Young, Chip Scale Packaging Provides Known Good Die, Proc. NEPCON West, pp. 52-62, 1995.

D28. J. E. Kohl, C. W. Eichelberger, S. K. Phillips, and M. E. Rickley, EPIC CSPÔ Assembly and Reliability Methods, The Technical Conf. at Chip Scale International ´98, Conf. Proc. Day 1, pp. 129-134, 1998.

D29. S. Baba, Y. Tomita, M. Matsuo, H. Matsusha, N. Ueda, and O. Nakagawa, Molded Chip Scale Package for High Pin Count, Proc. 46th ECTC, pp. 1251-1257, 1996.

D30. Y. C. Teo, T. B. Lim, H. M. Ho, C. Q. Cui, C. Tsui, S. C. Lian, and T. T. Tan, Low Cost Chip-Scale Package, Proc. 47th ECTC, pp. 358-362, 1997.

D31. J. Kasai, Low Cost Chip Size Package Solutions for ASIC and Memory Applications, Proc. Semicon/Europe Tech. Prog., 1996.

D32. C. M. Val, A. Ripart, and Y. Van Campenhout, New Chip Scale Package for Medical Applications: <<PLIP-CHIP>>, Proc. ISHM ’96 Symp., pp 236-242, 1996.

D33. J. Kasai, K. Tsuji, Y. Yoneda, S. Orimo, R. Nomoto, H. Sakoda, and M. Onodera, Development of Micro BGA and QFN by Leadframe Terminal Formation Method, Proc. First Pan Pacific Microelectronics Symp., pp. 23-30, 1996.

D4.3 Standards

J-STD-012, Implementation of Flip Chip and Chip Scale Technology, The Institute for Interconnecting and Packaging Electronics Circuits (IPC), January 1996. (http://www.ipc.org)

J-STD-020, Moisture/Reflow Sensitivity Classification of Plastic Surface Mount devices, October 1996.

Official representative proposal

J-STD-027, Mechanical Outline Standard for Flip Chip or Chip Scale Configurations

J-STD-028, Performance Standard for Flip Chip/Chip Scale Bumps

J-STD-029, Test Methods for Flip Chip or Chip Scale Products

J-STD-030, Qualification and Performance of Flip Chip Underfill Materials

J-STD-031, Mechanical Outline Standard for Ball Grid rays and other High Density Technology

J-STD-032, Performance Standard for Ball Grid Array Bumps and Columns

Working Draft

J-STD-033, Packaging and Handling of moisture Sensitive Non-Hermetic Solid State Surface Mount Devices

J-STD-035, Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Components

IPC-7076, Sectional Requirements for Chip Scale and Chip Size Component Mounting

D4.4 Conferences

Surface Mount International: http://www.smta-international.com

IPC National Conferences: http://www.ipc.org/html/framesetEAEexpo.html

SEMI Technical Proceedings: http://www.semi.org

NEPCON: http://nepcon.reedexpo.com

CHIPCON: http://www.semitech.com/chipcon/index.html

APCON: http://www.semitech.com/apcon/index.html

D4.5 Companies

Amkor/Anam: http://www.amkor.com/assembly_and_test/products/chipscale/index.htm

ChipScale Inc.: http://www.chipscale.com

Flip Chip technologies: http://www.flipchip.com/electron.htm

Fujitsu: http://www.fujitsu.co.jp/hypertext/Products/Device/CATALOG/AD81/81-00001/8e-2.html

Hitachi Cable: http://www.hitachi-cable.co.jp/microbga/index.htm

Kyocera: http://www.kyocera.com/kai/csp.html

LG Semicon: http://www.lgs.co.kr/pkgdev/index.html

Tessera: http://www.tessera.com/