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Chapter D: Chip Scale Packaging
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D2. Level 2. Conclusions
and Guidelines
D2.1 Technical Issues
D2.1.1 Basic properties of CSP packages A large number of CSPs have been described in the literature. Some key features for various CSPs are presented in Table D2. Table D2. Data summarised for various CSPs.
A comparative table of various technologies for a 100 lead 10x10 mm die is given in Tables D3 and D4 including dimensional and electrical properties. Table D3. Comparative figures for various technologies (from Ref. D1).
Table D4. Comparative figures for various technologies (from Ref. D4)
Due to the construction of many CSPs, the junction-to-case thermal resistance of a CSP is usually lower than that of a conventional plastic package. However, due to the small size, the junction-to-ambient thermal resistance is greater. According to Steve Greathouse at Intel [D4], CSPs can handle die that dissipate 0.5 to 2 watts depending on type and materials used. At higher power dissipation, heatsinks, heatspriders, thermal vias in the boards, increased airflow, or other options must be used. This will increase the overall size requirements considerably which may lead to that size and cost savings may be lost. Table D5 shows some techniques for heat dissipation. Table D5. CSP heat dissipation techniques [D3].
Qualification of packages are normally performed according to a number of standardised tests, such as those found in MIL-STD-883 [D5] and JEDEC Standard No. 22 [D6]. Some of the most used tests are listed in Table D6. Table D6. Common tests used for qualification of packages [D3].
Published results from qualification testing of various CSPs are given in Table D7. Table D7. Published results from qualification testing of CSPs [D7].
During recent years, the traditional way of qualifying components has been questioned since it has become evident that it is not enough for assuring reliability of products using new technologies. For qualification of packages, JEDEC has published a standard entitled "Failure-Mechanism-Driven Reliability Qualification of Silicon Devices" [D8] which is presented as an alternative to traditional stress-driven qualification. It is pointed out that in order for the standard to reach its full effectiveness, the original equipment manufacturers (OEM) and the supplier must develop partnerships. The OEM should accept the reliability qualification process performed by the supplier, per the guidelines of the standard, in lieu of the specific (special) reliability qualification process that many OEMs require today. The key issues in this process are to identify the crucial failure mechanisms (physics-of-failure) that will determine the reliability of a CSP and how to appropriately accelerate these failure mechanisms in reliability tests. Since reliability testing has to be application specific, it will not be possible to have a number of fixed reliability tests to chose between for reliability evaluations. In most cases, existing test methods have to be altered in order to be adequate or new test methods have to be developed. Furthermore, the very large variation of technologies used for constructing chip scale packages make it impossible to handle CSPs as a homogenous group when discussing reliability aspects. Since many of the technologies used are newly developed and unproved, one can expect that new types of failure mechanisms will arise for many of the package types. Since for most applications, the major reason for failures is the large difference in coefficients of thermal expansion (CTE) between silicon (chip) and printed board substrates, another classification than the previously described will be used when discussing reliability aspects of various CSPs in this section. It is based on how the design of the packages will affect stress distribution and failure mechanisms due to CTE mismatches between silicon and printed board substrate. This will, of course, also be affected by the type of printed board substrate used. If ceramic boards are used, the difference in CTE between the chip and the ceramic substrate will be small but, of cost reasons, this is not a viable alternative for most applications. Components with leads There are a few CSPs having leads, for example Hitachi Cable’s LOC-CSP [D9]. The leads will provide compliance that will decrease the stresses of the solder joints and the connections inside the package. The amount of stress reduction will depend on the stiffness and configuration of the leads. The basic feature of the LOC-CSP is similar to a PLCC component and it can therefore be expected to have good reliability properties, especially since it is intended for low I/O counts, i.e. small dimensions. There will be no need to use underfills to improve reliability. Packages with rigid structure and solder lands The most typical characteristics of this type of package are the rigidity and the very low CTE. Examples are Matsushita’s CSP [D10] and Toshiba’s CSTP [D11] with solder lands, both using ceramic substrates. Also ShellCase’s Shell-BGA [D12] with solder lands can be included in this package type. The rigid structure of these packages and the very low stand-off will cause extremely high stresses of the solder joints when exposed to temperature changes if they are soldered to organic printed boards. Therefore, they will mainly be used on ceramic printed boards. Packaged with small dimensions may be used on organic substrates for applications used in less demanding conditions. Use of underfill may extend the application fields. Packages with organic structure and solder lands This type of packages have solder lands created either by molding a lead frame into a resin or by plating the solder lands onto an organic laminate material. As for the package with rigid structure, high stress levels can be expected in the solder joints between packages and printed boards, but the organic resin in the package will give some flexibility to the package that will reduce the stresses in the solder joints somewhat. However, this will cause that cracking may also occur within the packages and the printed boards when organic boards are used. For this reason, the package type will only be suitable for small sizes, i.e. low number of I/Os, and less demanding conditionings. Use of underfill will improve reliability. Example of packages of this type are Amkor/Anam’s ChipSOP™, Express Packaging Systems’ NuCSP [D13], Fujitsu’s SON package [D14], LG Semicon’s BLP [D15], National Semi’s PCC [D16], and Silicon Systems’ ULTP [D17]. All these packages have terminals located along the periphery of the packages. Packages with ceramic interposer and solder balls This type of package is similar to the packages with rigid structure and solder lands, except for that the use of solder balls gives a higher stand-off for these packages that will improve reliability. The use of a ceramic interposer will prevent that stresses are distributed into the package. Still, the large difference in CTE for ceramic materials compared to organic laminate materials will make the use on organic printed boards questionable for demanding conditions. Example of packages of this type are IBM’s Ceramic Mini Ball Grid Array package [D18], Fujitsu’s Ceramic fine Pitch BGA, Toshiba’s Fan-Out FBGA packages, and Kyocera’s ceramic CSP [D19]. Packages with organic rigid interposer and solder balls This type of packages has basically the same construction as Motorola“s OMPAC version of plastic BGA, except for the smaller dimensions. The chip is mounted on a laminate substrate, either using wire-bonding or flip chip techniques. The solder balls on the package will give some stand-off to the components that will result in an improved reliability compared to packages with solder lands. Also, the organic interposer will give some flexibility that will give a better reliability of solder joints compared to packages using ceramic interposers. On the other hand, the flexibility of the interposer will lead to an increased risk for connection failures inside packages. Amkor/Anam’s Chip ArrayŌ Package with solder balls, Citizen Watch’s Fine-Pitch BGA, Motorola’s SLICC [D20] and Oki Electric’s CSP are examples of this package type. Packages with flexible interposer and solder balls (rigid structure) This package type shows large similarities with the previous package type except for that a flexible interposer is used instead of a laminate. In some packages, wire bonding is used in order to make the connection to the chip, for example Sharp’s CSP [D21] and TI Japan’s Microstar BGAŌ . However, many packages are using new innovative methods for creating the connection to the chip which may result in the appearance of new failure mechanisms that must be considered when evaluating the reliability. Package with new interconnection methods are Fraunhofer/TU Berlin’s Flex-based CSP, General Electric’s TZOP [D22], NEC’s Fine-Pitch BGA [D23], Nitto Denko’s Resin-Molded CSP [D24], and Sandia’s mBGA [D25]. Packages with compliant layer In order to reduce the stress on the solder joints, some packages are constructed with a compliant layer. The most well-known package of this type is Tessera’s µBGA [D26],, but also ShipScale Inc.’s Micro SMT Package [D27] and EPIC technologies’ EPIC CSPŌ [D28] can be incorporated in this package type. The compliant layer will result in low stress levels of the solder joints making the use of underfill unnecessary even in rather harsh conditions. However, that is on the expense of increased movements in the compliant layer that leads to increased risk for failures within the package. Moulded chips with solder balls Mitsubishi Electric’s Moulded CSP [D29] and Singapore’s Institute of Microelectronics’ CSP [D30] consist of bumped chips that have been plastic moulded. Solder balls have then been attached to the bumps. The similarity of these packages to flip chip is large. However, the larger stand-off for these packages will give better reliability than flip chip. Despite that, underfill will probably be necessary for many applications in order to get acceptable reliability. Packages with metallised polymeric bumps An increased stand-off can be achieved by using metallised polymeric bumps or posts on the package. It is an interesting to give compliancy to the connections but have only been achieved along the periphery of components. The limited experience of this type of connections make it difficult to predict the reliability and dominant failure mechanism. Example of packages of this type of packages are Fujitsu’s Resin-Bump SON CSP [D31] and 3-D Plus’ Plip-Chip CSP [D32]. Packages with metallic bumps Some packages have what could be characterised as metallic bumps or studs, for example Fujitsu’s Micro BGA and Lead Frame QFN packages [D33], and Hitachi Cable’s µstud BGA Package. These packages are very disparate and, as for the previous group, difficult to predict the reliability and dominant failure mechanism.
D2.2.1 Design rules and compatibility Since only a few companies are using CSPs in their products, little experience is available about production issues. For CSPs with grid array structures, some of the experience gained from BGA technology is valid. However, for CSPs with small pitches and/or large number of I/Os, routing will be difficult. Some extra space can be gained by using via-in-pad. However, for many application areas, it will be necessary to use high-density boards such as microvia boards. J-STD-012 recommend to use solder mask defined lands [D1]. Solder mask defined lands have been found to reduce reliability of BGAs (See BGA Chapter E.2.2.1). No studies have been reported of how they affect the reliability of CSPs. For some CSPs without a compliant structure, it will be necessary to use underfill in order to get acceptable reliability when mounted on organic printed boards. Most CSPs can be mounted using current fine pitch SMT assembly materials and processes. Vision systems may have problem recognising the structure of some CSPs. In addition, some packages are moisture sensitive. That is, they must be stored in dry conditions and used within a specified time frame after they have been exposed to humid environments. If the time frame is surpassed, or if a package needs to be reworked, it should be baked before any work is performed. In general, the same criteria is applicable for CSPs as for BGAs and QFPs (See BGA Chapter E2.2.3). As pitches for CSP may get smaller conventional pick & placement machines may not suffer for mounting of the components which then will necessitate investments in new machines. Also, X-ray equipment my be necessary for inspection for verification of solder joints. In cases when underfills must be used of reliability reasons, material and equipment for the underfilling process will add to the total cost. See also the BGA Chapter E2.2.2. D2.2.4 Inspection and Workmanship Standards Generally the same apply to CSPs as for BGAs (See the BGA Chapter E2.2.4). Generally the same apply to CSPs as for BGAs (See the BGA Chapter E2.2.5).
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