Bumping and UBM processes

Various bumping processes suited for flip chip soldering have been reviewed e.g. by Patterson et al [B3]. The main wafer level bumping processes are evaporated solder bumping, electroplated solder bumping and printed solder paste bumping. Solder ball bumping using slightly modified ball bonder and wire of solder alloy material have also been used.

The deposition of under bump metallurgy (UBM) on to the pad areas of the chip is a very important issue to allow bump formation and to stand the flip chip soldering process. The under bump metallurgy has various functions. It must allow good enough adhesion to the pad metallisation which usually is aluminium. It must act as a diffusion barrier during the soldering process, allow good wettability of the solder material and prevent oxidation of the surface. For different bumping processes different under bump metallurgies are used. Table B1 summarises the features of each solder deposition processes in terms of under bump metallurgy.

In evaporated solder bumping process a metal mask (typically molybdenium) is used to make the deposition of UBM layers and the solder alloy onto a silicon wafer with normal passivation as well as polyimide passivation (see Figure B8). The process includes sequential evaporation of chromium, a phased chromium/copper layer, a copper layer and a gold layer to form the UBM. A high lead solder layer is then evaporated on top of the UBM to form a thick deposit of 97PbSn or 95PbSn.

Figure B8. Evaporative solder bumping process [B3].

Electroplating is a popular alternative to the evaporation process because of its lower cost, facility and floor space requirements. One of the various process alternatives is schematically shown in Figure B9. The UBM materials used are typically TiW, Cu and Au sequentially sputtered or evaporated over the entire wafer. The UBM adheres to the wafer passivation as well as to the bond pads. Patterned photoresist is then applied to allow plating of copper minibump onto the UBM metallisation. A second mask allows then the formation of the plated solder bump, after which the photoresist is stripped. The UBM which is on the entire wafer is removed from the areas other than pad areas by wet etching. Finally the bumps are formed by reflow

Figure B9. Solder bumping by electroplating process.

The formation of the bump by stencil printing of solder paste is a practical process which is suited for many types of solder materials including 63SnPb. The UBM layers are deposited by sputtering. The first layer is sputtered aluminium followed by sputtered layers of Ni and Cu. A layer of photoresist is applied, patterned and developed. The Al, Ni and Cu-layers are then etched away except over the bond pad passivation openings. The photoresist is removed leaving the UBM over the pad areas. Solder paste is then printed onto pad areas and reflowed to form the spherical bumps.

Figure B10. Sputtered UBM and solder paste bumping process.

The company Flip Chip Technologies has design guide (http://www.flipchip.com), which gives advice for selecting between available bumping materials, explains the geometrical restrictions and die pad design standards, bump placement, resistance and shear test patterns, alignment key specification and placement as well as wafer passivation requirements. Various test die (peripheral or array type) and substrates available for evaluation and reliability testing. Compatibility of the solder material with the substrate material is very important. FR4-substrate, for example, can not stand the high temperature reflow temperature of Pb95/Sn5. If high temperature solder is used for bumps, low temperature solder alloy must be applied to the substrate to make possible a low temperature joining process. The minimum pitch obtained for perimeter pad layout is about 200 m m whereas for the area array layout the minimum pitch is about 250 m m.

In almost all dies the pads are peripherally located because of the wire bonding applications. For flip chip bonding the number of I/O can be increased by applying area array pad layout. The redistribution of the pad layout from peripheral arrangement to area array arrangement is possible by doing extra redistribution circuitry onto the die prior to bumping process.

Maximum current density for solder bumps is approximately 4200 A/cm². Typical bump heights are 125 - 140 m m depending of pitch and the bump height tolerance ± 15 m m.

Substrate metallization

The metallization on the substrate must be solderable to the solder material used in the bumps. If the matching lands on the substrate are copper, they are usually plated with tin-lead, tin or gold. If gold is used as the metallization on the substrate, its thickness should be limited to 1 - 2 m m in order to limit the formation of brittle gold-tin intermetallic compound. If bare copper is the metallization, it may be desirable to coat the lands with molten solder by a solder levelling process to improve solderability and increase the volume of solder for a more compliant joint. However if such a process is used, care must be taken to insure uniformity of deposited solder height and volume among all the lands for a given chip, since deviations greater than 50 m m may lead to open circuit conditions after the reflow assembly process step.

Heat

Maximum recommended junction temperature is 140 ^oC without underfill and 150 ^oC with underfill. The thermal resistance for one joint is 1000 - 1500 ^oC/W. The thermal resistance from chip to substrate through the flip chip joints may be roughly obtained by dividing the thermal resistance of one bump by the number of bumps in the chip. This is the worst case situation because there are also other routes of heat flow which may affect the cooling of the chip. Extra dummy bumps increase the cooling efficiency. High thermal conductivity underfills can be used. When efficient cooling is needed like in high power processor packages back side of the chip can be used for thermal management of the package [B4,B5].

In a 144-pin plastic pin grid array (PGA) package containing a flip chip bonded 10 x 10 mm silicon test die with 82 peripheral bonding pads bumped with 97%Pb3%Sn solder bumps allowable power dissipation in the package was found to be between 1.7 and 6.7 W in free air and between 2.1 and 13.7 W in air flowing at speed of 1.27 m/s. The highest power ratings were possible using a heat sink connected to the lid of the package and a thermal pad between the chip and the lid. The inclusion of underfill material did not enhance the package thermal performance significantly [B6].

Speed

The flip chip assembly is ideal for high frequency applications because of the very short current path between the component and the substrate. For solder joined flip chip connections the joints are metallurgical joints with series resistance of the order of 1 mW . The series inductance is very much smaller than that of wire bonded joint or leaded package. For typical leaded package the series inductance is from 5 to 10 nH while that for flip chip solder joint is only about 0.025 nH. Because of the smaller capacitance, smaller inductance and smaller resistance of the flip chip joints compared with wire bonded joints the propagation delay is also considerably smaller in the flip chip structure. In Table B2 there is a comparison of inductance, capacitances, resistance and propagation delay in two types of packages: Pin grid arrays (PGA) with wire bonded chip and ball grid arrays (BGA) packages with flip chip bonded chip. [B7]. The bumps represent the main discontinuity to the signal propagating on the line which results in partial loss, reflection and possibly distortion of the signal. In principle the bump dimensions can be used as impedance matching parameters to achieve minimum losses over a wide frequency band [B8].

Noise

Generally there are good reasons to assume that solder joints used in flip-chip joining do not generate harmful noise. In digital CMOS processor designs the power supply noise is determined by the core and input drivers and by their ability to draw instantaneous current from the supply and on the way how the on-chip power distribution structures interact with the package and board design. As reported by H. Hashemi and D. Herrell [B9] the flip chip connections, when compared to the wire bonded design, improve the power disturb performance by at best a factor of two. This is because the on-chip and on-package power grid distribution inductance can dominate the low inductance of the flip chip connections. They found that on-chip decoupling capacitors in conjunction with a substantial on-chip power grid structure can provide a much lower noise environment for both wire bonded as well as flip chip connected devices.

Reliability

The main reliability factor is thermal fatigue of solder joints. Other possible failure mechanisms are corrosion at the joints or metallisations and migration of atoms caused by electric fields or thermal gradients in the structure. Alpha particles can be a possible cause of failures for memory chips.

Thermal fatigue depends strongly on the solder material, on the thermal expansion difference of chip and substrate, the height of solder joint and on the distance of solder joint from the neutral point of the joined structure as well as on the range of temperature changes in the environment. The underfill material used between chip and substrate increases drastically the reliability of the joints for thermal fatigue. The thermal fatigue behaviour of different solder compositions are compared in table B3. Indium based solders which are fatigue-resistant are, however, not reliable in high-humidity environments.

Thermal fatigue of solder joints is an important reliability issue for flip chip joining when no underfill material is used. Properly selected underfill material blocks out part of the thermally induced deformation in the joints to such an extent that the fatigue damages are no more clearly dependent on the distance of the joint from the neutral point of the structure. By taking stress into itself the underfill material transfers part of the deformation to deformations in the chip and substrate. In some cases the stress in the chip may become large enough to cause cracking of the chip. The amount of die stress depends mainly on substrate material and on surface quality of the silicon die [B11]. FEM-analysis methods for reliability estimation [B12], empirical reliability modelling equations [B13] or available PC-software tools [B14] can be used to life time estimation of solder joints in cyclic temperature variation. For critical applications comparative accelerated reliability tests are recommended [B15].

Testing

The flip chip bonded components should be tested before the curing of underfill material. Once the underfill material has been cured the removal of a faulty chip is extremely difficult. Testing of the ICs even prior to flip chip bonding is desirable because joining of functional components (i.e. known good die) minimises the need for rework.

There are still some technical and infrastructure obstacles with known good dies which need to be overcome. Traditionally ICs are tested fully and burned-in after packaging since it is much easier to perform final testing of the chip in its package form. From a business standpoint most companies are not interested in selling bare die since part of their profit is derived from the package and it is difficult to guarantee the quality of bare dies [B16].

There are basically two ways to test and burn-in for the known good dies: (1) at the wafer level and (2) at the individual chip level. Because of the power distribution, cooling and wafer contact problems, test at high speed and burn-in of chip at wafer level poses a technical challenge. Testing of individual dies has several challenges, too. Test at high speed and burn in for individual bare chip using sockets, probe cards etc. may damage the pads on the chip, limit high frequency capability and increase cost. Built-in self testing (BIST) chips and boundary scan test of innerchip connections are under active investigation [B17].

Maintaining electrical connections to a large array of soft solder bumps can be extremely difficult. Since the mechanisms that cause the connections to fail are accelerated by increased temperature, the connections can be even less reliable than the ICs being tested. The net result is that the data collected from burn-in is contaminated or even dominated by connection failures. One approach to minimise these failures is to use Burn-in and test substrate (BATS) method that has been developed by MCNC Electronic Technologies Division. The BATS method provides a temporary metallurgical connection between the flip chip IC and a reusable carrier. The first generation of BATS is a multilayer ceramic substrate with a cofired thick-film metallurgy that is not wettable by PbSn solders. The top surface is patterned with an array of pads matching the pattern of the IC to be tested. Prior to mounting an IC to the BATS, a thin layer of sacrificial metal is deposited over the nonwettable top surface pads. An IC is then placed on to the substrate and solder reflow is performed resulting a metallurgical joint. Because the connection is a true solder joint, all the requirements for a flip chip testing and burn-in solution are met. After testing and burn-in, the BATS assembly again undergoes the reflow process, at which time the sacrificial metal dissolves into the solder bump, leaving the solder in contact with the nonwettable co-fired metallurgy. This causes the solder to dewet from the substrate surface and the IC can be removed from the substrate. After the IC is removed from the BATS, the sacrificial metal is redeposited and the test substrate is ready for reuse [B19]

The difficulty in bare die testing and burn-in results in extra cost and therefore known good dies are usually more expensive than packaged components. Some semiconductor manufacturers also offer die products that have been only minimally tested. These dies are offered in volume at prices that are below packaged part’s pricing. On the other hand, the manufacturers do not guarantee specific yields for these minimally tested bare dies [B20].

Figure B11. Flip-chip assembly line containing a separate flux dispensing unit. (Photo courtesy of Asymtek.)

For some applications such as chip-on-glass for displays, soldering might not be a preferred technology, and alternative approaches have been developed. Most of solderless flip chip technologies connect a component to a substrate through adhesive, thermocompression or thermosonic bondings. These technologies posses the following advantages: 1) a simple, fluxless, dry process, 2) a low processing temperature, 3) a high operation temperature, 4) no lead. content, and 5) very fine-pitch connections.

Bumping

The preferred bump material for thermocompression flip chip bonding is gold. These bumps can made using the conventional electrolytic gold plating (used for TAB bumps) or the stud bumping method. The gold ball bumps (see Figure B13) are fabricated with a flexible low cost bumping technique based on the conventional wire bonding procedure. Established wire bonding machines can be used; therefore, expensive bumping process equipment for sputtering lithography and plating is not necessary. The gold wire must be alloyed with 1% Pd to ease the breaking of wire above the bump. During bump formation the wafer/substrate must be heated to 150... 200° C.

Figure B13. SEM-image of a stud gold bump.

Substrate metallization

The pads on the substrate must have a correspondingly bondable metallization, e.g Au-plating or aluminium (silicon substrates). Additionally, the substrates must have a high planarity.

Heat

See the Flip chip bonding using soldering process/Heat chapter

Speed

See the Flip chip bonding using soldering process/Speed chapter

Noise

See the Flip chip bonding using soldering process/Noise chapter

Reliability

The critical factors determining the reliability of thermocompression bonded chips are similar to bonding with solder joints, e.g. the difference of TCEs between the chip and the substrate, the height of joints and the maximum distance between joints. It is likely that most of the damages (cracks) to the bond area are created during the cooling from the high bonding temperature. The susceptibility to fatique damage of gold is much lower than that of solder due to its much higher melting temperature, so if the adhesion strengths between the bump and the pads are not exceeded during thermal cycles the reliability would not be a problem.

The underfill material used between chip and substrate increases drastically the reliability of the joints for thermal fatigue. Thermal fatigue of joints is an important reliability issue for flip chip joinings where no underfill material is used.

Testing

A flip chip bonder capable of producing the high bonding temperature of 300° C and force of up to 100cN/bump, and with high accuracy in the parallelism alignment is required (this depends, of course on the pitch). In order to avoid predamaging of the semiconductor material, the bonding force must be applied with a gradient. For brittle GaAs devices an optimal gradient of 5-10 cN/s has been found.

In order to achieve good bonding during thermal compression flip-chip attach a certain amount of ball-bump deformation is necessary. On the other hand, the bonding force and temperature should be as low as possible in order to prevent damage of chip and substrate. For example, for GaAs chips the following parameters have been reported for attaching on silicon substrate: bonding temperature 320° C and bonding force 25-100cN/bump. On GaAs the bonding pads were of Al, on the silicon substrate different type of metallisations were investigated: 1m m AlSi, 0.4m m Au or 2m m electrolytic Au.

Figure B14. Example of flip chip bonding parameters for TC bonding of GaAs devices.. Stage temperature 320° C, bonding temperature 320° C, max. bonding time 15 s, force gradient 5/10 cN/s [B21].

Bumping

The preferred bump material for thermocompression flip chip bonding is gold. These bumps can made using the conventional electrolytic gold plating (used for TAB bumps) or the stud bumping method. The stud bumps are fabricated with a flexible low cost bumping technique based on the conventional wire bonding procedure. Established wire bonding machines can be used; therefore, expensive bumping process equipment for sputtering lithography and plating is not necessary. The gold wire must be alloyed with 1% Pd to ease the breaking of wire above the bump. During bump formation the wafer/substrate must be heated to 150.. 200° C.

Substrate metallization

The pads on the substrate must have a correspondingly bondable metallization, e.g Au-plating or aluminium (silicon substrates). Additionally, the substrates must have a high planarity.

Heat

See the Flip chip bonding using soldering process/Heat chapter

Speed

See the Flip chip bonding using soldering process/Speed chapter

Noise

See the Flip chip bonding using soldering process/Noise chapter

Reliability

The critical factors determining the reliability of thermosonic bonded chips are similar to bonding with solder joints, e.g. the difference of TCEs between the chip and the substrate, the height of joints and the maximum distance between joints. It is likely that most of the damages (cracks) to the bond area are created during the cooling from the high bonding temperature. The susceptibility to fatique damage of gold is much lower than that of solder due to its much higher melting temperature, so if the adhesion strengths between the bump and the pads are not exceeded during thermal cycles the reliability would not be a problem.

The underfill material used between chip and substrate increases drastically the reliability of the joints for thermal fatigue. Thermal fatigue of joints is an important reliability issue for flip chip joining when no underfill material is used.

Testing

The adhesive flip chip joining with isotropically conductive adhesives is different from joining with anisotropically conductive adhesives. Therefore the following text is sometimes divided into two parts (ICAs and ACAs). Joining with nonconductive adhesives is not covered because its practical use has so far been very limited. In theory, joining with nonconductive adhesives is very reliable because it decreases the bonding interfaces to a minimum. The situation is different in practice, however. The process is difficult to handle and the joints suffer from reliability problems. For example, the planarity requirements for substrates are much more critical when bonding with nonconductive adhesives than when bonding with ACAs and ICAs.

Bumping

Figure B16. SEM-photograph of a polymer bump made with isotropically conductive adhesive. The bump height is approximately 45 m m.

Heat         Also look at Polymer Bonding Section C2.3.2

Both ICAs and ACAs are inferior thermal conductors when compared with tin-lead solders. The thermal conductivity of ICAs ranges between 2 and 10 W/m× K. For ACAs the thermal conductivity is around 1 W/m× K. Tin-lead solders have a thermal conductivity between 35 and 50 W/m× K. In practice, however, the thermal resistance of a component is not increased by much if solder flip chip bonding is replaced by adhesive flip chip bonding. Only a small amount of the generated heat in a component is transferred through the flip chip joints and the thermal resistance is governed by other factors such as chip size and substrate material, see 2.1.1.

Speed        Also look at Polymer Bonding Sections C2.3.1 and C2.3.13

The electrical conductivity of ICAs and ACAs is also inferior to tin-lead solders. ICAs have about one magnitude greater volume resistivity than eutectic tin-lead solder (R_vol=170× 10^-6 W × cm). The studies at VTT Electronics have shown that the resistance of an ICA flip chip joint is in the range of a few milliohms. [B24] There is no literature available on adhesive flip chips joints inductance or capacitance. However, it can be estimated that the use of ICAs will somewhat increase the electrical values in Table B2.

For ACAs no volume resistivity is given, because the adhesive is not conductive until it has been used to join two surfaces. The use of ACAs has been popular in joining fine pitch heat seals and other such connectors for almost a decade. Such applications do not require minimal electrical resistance. Research has also shown that ACA flip chip joint can have adequate electrical resistance for component joining [B25].

There is ongoing research on the rf-properties of adhesive joints at IVF and some of the results have already been published. For low frequency applications (500 MHz-8 GHz) the results indicated that the ACA flip chip joint and the bridge joint mounted on the FR-4 board or the flexible board can be used. For high frequency applications (1 GHz-40 GHz) the results showed that the ACA flip chip joint and the bridge joint mounted on the high frequency teflon based duroid substrate can be used [B26].

Noise

The noise properties of adhesive flip chip joints have not been widely researched. Solder joints are low noise joints and it is speculated that the use of adhesives will increase the noise in a flip chip joint. On the other hand, this noise increase may not have any affect on the components performance.

Reliability        Also look at Polymer Bonding Sections C2.5   and C2.6  and C2.3.13

Figure B17. The effects of ageing at 85%RH/85°C on the junction resistance of ICA joints of Au- and Ni-plated components bonded on to thick film Au-metallisation. These results are from die bonded components.

In contrast to ACAs, where most failures are accelerated by humidity testing, temperature cycling is more critical for ICAs. Failures occurring at thermal cycling tests are introduced by component’s and substrate’s different thermal expansion coefficients. This results shear strain inside the adhesive layer. In case of ICA the stresses may lead to an adhesion failure of single bumps. Fortunately, the use of an underfill material drastically increases the reliability of an ICA flip chip joint (Figure B18).

Figure B18. The resistance of adhesive joint as a function of the number of temperature cycles between temperatures –40 ° C and 120 ° C. The components have Au-stud bumps. They have been flip chip bonded with an ICA and underfilled [B28].

Testing

Figure B19. Stud bump adhesive joining process.

The bonding process is a little different for thermosetting ICAs and for thermoplastic ICAs The thermoplastic polymers consist of long polymer chains and therefore the rheological properties of the adhesives have to be modified with a substantial use of solvents. These solvents often need to be dried after the adhesive has been applied onto the flip chip bump. After drying the adhesive it is possible to store the components or substrates and make the adhesive bonding later, perhaps even in some other factory. When thermosetting adhesives are used the time span between adhesive application and chip placement should be as short as possible.

To cure a thermosetting material a transfer of energy into the polymer is required. This energy is usually supplied by external heat from an oven. During the curing process no pressure is needed to keep the components in place. The curing temperature ranges typically from 80 ° C to 200 ° C and the cure time from 5 minutes to some hours. Adhesives usually have many optional cure schedules. A common rule of a thumb is that a decrease of 10 ° C or 20 ° C in curing temperature doubles the cure time. To cure the adhesives also infrared or ultraviolet energy can be used.

Bonding with a thermoplastic adhesive is a heat/pressure process. Flip chip bonding typically lasts some seconds. The adhesive manufacturers supply instructions of the suitable heat, pressure and time. As the attach temperature rises, the attach pressure and time can be decreased. Thermoplastic adhesives can bond over a broad process window-as low as 100 °C and up to over 300 °C. Bonding limits lie between the glass transition temperature of the polymer and its decomposition point. Applied pressure forces the softened or liquefied polymer into the surface microstructure of the adherents, producing a mechanical link. The time factor, or dwell, allows heat to distribute at the interface and the fluid polymer to penetrate to surface microstructures. The triad key of bonding parameters, temperature, pressure and time are interactive as mentioned earlier, but they are also non-linear. Temperature has the most pronounced effect.

After flip chip joining with ICAs an underfill material can be applied. In practice the use of an underfill material is necessary because the bonding strength of ICA joints is seldom enough to reliably hold the chip in place.